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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Issue 4 • Date Dec. 1990

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Displaying Results 1 - 25 of 78
  • Optical and electrical investigation of ion bombarded GaAs

    Page(s): 617 - 622
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    (100) surfaces of GaAs were bombarded with low energy Ar+ ions at energies to 4 keV. Photoconductivity and Schottky diode studies were then performed. A striking persistent photoconductivity that was observed is attributed to an optically and temperature sensitive metastable defect complex formed by the ion beam etching (IBE). Optical quenching of spectral conductivity, restorable by thermal activation at temperatures above 120 K, is also attributed to this complex. Photovoltaic response of Schottky diodes is essentially destroyed by IBE damage for all ion energies. The IBE caused damage is also seen in low frequency capacitance dispersion; none is evident for the virgin (no IBE) case. Two electron traps resulting from IBE, at 0.32 and 0.52-eV energies, were detected by deep level transient spectroscopy (DLTS). The IBE caused disappearance of the EL2 trap at 0.76 eV is consistent with the formation of EL2-IBE related complexes at lower energies in the bandgap, which can account for the persistent photoconductivity and low frequency capacitance dispersion. View full abstract»

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  • Automatic testing of metallized ceramic-polyimide (MCP) substrates

    Page(s): 822 - 827
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    The automatic testing and handling of MCP substrates at IBM is discussed. After a brief description of the product and the manufacturing processes, the challenges of testing the product, the defect mechanisms, automatic product handling, the test electronics, computer control, and alternative ways to contact the part are discussed. Every substrate is electrically tested twice. It is tested once after all of the photolithographic and wet processes, but before pinning and tinning (midline test) and once before it is put to stock (end-of-line test). The handler and electronics of the end-of-line tester are discussed. The mid-line tester is in many ways similar to the end-of-line tester. The differences between mid-line and end-of-line testing are briefly outlined View full abstract»

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  • Mechanical engineering issues and electronic equipment reliability: incurred costs without compensating benefits

    Page(s): 895 - 902
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    Temperature is widely viewed as a major influence on failures of electronic equipment. The failure prediction methodology (FPM) concept of a constant failure rate that is accelerated by various environmental influences is widely applied beyond its validity. Misapplications of the reliability models in current use may cause failure avoidance efforts such as temperature reduction and parts quality selections not to yield anticipated overall results. The cost and complexity effects can be significant: temperature reduction, for example, can result in expensive system implementations in some cases. The author feels that the continuing quest for electronics reliability should change emphasis from attention to electronic parts to activities that address assembly and processes and he discusses the ways in which the temperature ingredient of reliability and similar concepts can be currently applied. Examples to illustrate disparities between anticipations and realizations are given. Alternate approaches are offered and their possible implementations are discussed View full abstract»

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  • GaAs multichip module for a parallel processing system

    Page(s): 828 - 832
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    The module described is a high-speed data transfer network for a parallel processing system. The high-speed data transfer network connecting multiple processor units was realized in a module using 8-bit slice GaAs bus logic (BL) LSIs which operate at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3×4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to a copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin film termination resistors are made of Ni/Cr in the substrate to prevent reflections. Heat generated from the module, which has a total of 90 W of power dissipation, is transferred through four heat pipes with fins by forced-air cooling at <2 m/s. A 3-Gbit/s data transfer rate can be realized by four stacked modules of 38 GaAs BLs View full abstract»

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  • Characteristics of heat transfer in small disk enclosures at high rotation speeds

    Page(s): 1006 - 1011
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    Experimental results are reported for heat transfer in small disk enclosures containing several 5.25-in-diameter disks and two symmetrical brushless DC motors mounted on a spindle. The air flow over the disk is probably turbulent at a rotation speed of more than 5400 r.p.m., and windage loss dominates the total rotation loss. Effective forced convection reduces the temperature increase inside the enclosure. There is not much temperature dependence on disk position, because heat generation in the enclosure is symmetrical. Track densities of more than 100 tr/mm are shown to be feasible as a result of the small thermal off-tracking and head position deviation View full abstract»

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  • High performance screen printable silicone as selective hybrid IC encapsulant

    Page(s): 759 - 765
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    A solvent-, flux-, and detergent-resistant screen-printable silicone (SPS) with a modest curing temperature and excellent adhesion to gold-plated substrate integrated circuits is described. The material formulation and need for an encapsulant with the above properties is described. Microdielectrometry was used to define the precise SPS cure schedule. Temperature humidity bias was used to qualify the material's electrical performance. Auger spectroscopy and laser ionization mass spectrometry were used to further elucidate the crosslinking density and the interfacial interaction of the SPS and encapsulated substrate View full abstract»

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  • Computation of transients in lossy VLSI packaging interconnections

    Page(s): 833 - 838
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    An efficient method for analyzing the dynamic behavior of lossy electrical interconnects (with frequency-dependent parameters) in very large scale integration (VLSI) systems is presented. The method allows for the inclusion of electrical interconnects which are terminated by networks of lumped passive (R,L,C) and active nonlinear devices such as diodes and bipolar and MOS transistors. The method consists of deriving the circuit model for a transmission line from impulse response data and incorporating this model into an existing computer program called UANTL which performs time-domain analysis for coupled transmission lines with nonlinear termination. Several numerical experiments with this method were performed. Comparisons are made between the results obtained using this method and previously published results View full abstract»

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  • A review of thermal enhancement techniques for electronic systems

    Page(s): 1012 - 1021
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    Thermal enhancement techniques for maximizing the thermal contact conductance including the use of greases, metallic foils, and screens, composite materials and cements, and surface treatments are reviewed. The relative merits of the various enhancement techniques are summarized and comparisons are made for selected thermal enhancement materials. The results should prove useful in selecting thermal enhancement materials for use in improving the thermal performance of specific electronic systems View full abstract»

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  • Effects of polymer/metal interaction in thin-film multichip module applications

    Page(s): 766 - 774
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    The effects of different polyimide/metal combinations on structures similar to those used in thin-film multichip module applications were studied. Three different metal structures and three commercially available spin-on polyimide materials with differing molecular structures were examined. Transmission electron microscopy (TEM) was used to study the polyimide/metal interfaces. Measurements of the electrical signal propagation through the different polyimide/metal structures were compared. It was found that the extent of interaction of polyimide with copper is dependent on the type of polyimide used. The use of an electroless nickel layer over copper structures was found to retard copper/polyimide interaction during the curing cycle. The use of aluminum conductor lines with various polyimides was also examined. No significant interaction occurred between aluminum and any of the tested polyimides View full abstract»

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  • Flip-chip soldering to bare copper circuits

    Page(s): 656 - 660
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    A process for providing highly reliable high-yield controlled-collapse ship connection (C4) joining to bare copper circuitry is described. It was studied in the course of implementing a major change in IBM's metallized ceramic and metallized ceramic polyimide (MCP) production line. The study involved joining chips with 95/5 Pb/Sn C4 solder bumps to bare copper pads on substrates to replace dip-tinned substrates with 90/10 Pb/Sn coated pads. Included is an extensive analysis of the C4 intraconnection. Over 30000 chips were joined to ceramic substrates to characterize wetting to the copper pads, evaluate C4 fatigue life, and assess any reliability impact of natural and artificially induced defects in the C4 columns or wetted pad surface. Statistically, combining the self-removal of contaminants in C4 jointing, the small area a partial wet must have wet a pad, the location dependency for a failure, and the probability of contamination, there is no effect on product reliability View full abstract»

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  • Development of copper wire bonding application technology

    Page(s): 667 - 672
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    The continuous forming of oxide-free, stable, spherical copper balls which has been realized by blowing a reducing gas over the copper wire during copper ball formation (sparkling) is described. The prevention of chip damage resulting from hard copper wire, including underpad cracking and silicon cratering, by the double-load wire bonding technology is discussed; this technology can minimize chip damage from wire bonding stress because the bonding load is decreased during ultrasonic power oscillation. It was confirmed that copper wires have a reliability equivalent to that of gold wires. The double-load wire bonding technology makes it possible to use copper wires in MOS LSI devices on a commercial basis View full abstract»

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  • Transient thermal study of semiconductor devices

    Page(s): 980 - 988
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    An analytical, three-dimensional transient temperature solution of a two-layer semi-infinite plate structure with embedded hear sources is derived. The thickness of the second layer is assumed to extend to infinity. By incorporating the method of images, this solution can be used to approximate the structure with finite second-layer thickness. Exact temperatures can also be obtained for the rectangular lateral boundaries by the use of method of images. The derivation of the solution is verified by comparison with the steady-state temperature solution. A computer program has been written based on the solution and the method of images. A variety of device structures have been studied. Results for the thermal rise time and the effect of the second-layer medium are discussed. The software developed is particularly useful for devices operating under pulsed conditions or switching conditions View full abstract»

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  • A comparison of copper and gold wire bonding on integrated circuit devices

    Page(s): 673 - 681
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    A study carried out to investigate the process and material variables in developing a copper wire bond assembly process and to determine the potential performance and reliability of the finished product. A summary of Cu and Au comparison results for die bond, material selection, ball shear, and wire pull evaluations is given. The electrical and thermal performances are described. The intermetallics and reliability results are discussed View full abstract»

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  • Strength and reliability of ceramic modules soldered to flexible cables

    Page(s): 661 - 666
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    A study of the strength and reliability of soldered interconnections between module pins and flexible cables is presented. A quantitative measure of the strength of the connection is developed. Individual pins were mechanically tested by measuring the force required to push them through the cable. Both force and failure mode were recorded. The push-through test was used to determine optimum solder volume for maximum initial strength and also to measure degradation following exposure to environmental stresses. The first reliability stress was to store units at constant elevated temperatures of 80, 100, and 125°C for up to 8500 h. Analysis of these results was done with a nonlinear regression model. Since multiple failure modes were present, the data was deconvolved by treating it as multiply censored and analyzing it using maximum-likelihood techniques. The temperature dependence of the degradation rate was assumed to be Arrhenius. For the dominant mode, the results of this model are shown. The results give an effective activation energy of 0.6 eV. The second reliability test was to thermally cycle units between -40 and +100°C for up to 1000 cycles. There was no degradation. A simple first-order estimate indicates that this is equivalent to about five lifetimes View full abstract»

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  • In situ calibration of stress chips

    Page(s): 888 - 892
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    A special test chip having several silicon diffused piezoresistive strain gauges is described that was used to demonstrate an in situ calibration procedure for the gauges. It is based on the use of a high-sensitivity strain measuring technique called Moire interferometry to monitor mechanical strains at the location where the gauges are, thus providing a direct correlation between measured resistance changes of the gauges and actual strains. Many of the limitations and drawbacks of previous calibration techniques have been eliminated by this approach which is direct, simple, and reliable. It is applicable to new as well as existing stress chips View full abstract»

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  • High performance air cooled heat sinks for integrated circuits

    Page(s): 1022 - 1031
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    A simple, compact, high-performance air cooling technology is described that combines laminar flow with certain heat-sink designs to achieve a cooling performance of <2°C/W/cm2 at 2 ft 3/min. It has the capability to remove in excess of 600 W from a multichip module (25 chips at 25 W and 16% chip-to-substrate coverage) with a quiet 10-W tubeaxial fan. The volume of the complete module including the plenum and the fan is only about 1 l. The chips are held to maximum temperature rise of 55°C. Even higher cooling performance at greater chip-to-substrate coverage is shown to be possible with larger air movers. This technology extends the applicability of air cooling to the power levels of complex liquid-cooled modules View full abstract»

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  • Silicon interconnect-a critical factor in device thermal management

    Page(s): 946 - 952
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    The analytical and experimental methodologies for studying silicon device degradation under electrothermal stress are investigated. The experimental data support the assumption that the thermally induced stress due to power cycling and power surges is a major cause of device degradation. The analytical models point out the large impact that low-thermal diffusivity layers (solder or epoxy), located near the heat source (the thermal junction), have in the acceleration of fatigue phenomena. Crack initiation and propagation in die attach layers due to stress/strain cycles is shown to be one of the leading factors in degradation of power-cycled devices. The data were accumulated during the investigation of failure mechanisms of solid-state protection devices. From the degradation mechanism they observed, the authors conclude that the correct design or selection of the silicon device interconnect can increase device reliability and allow the device to operate at temperatures up to 125°C without increasing the field failure rate View full abstract»

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  • Damage in silicon caused by magnetron ion etching and its recovery effect

    Page(s): 629 - 632
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    Damage in silicon exposed to magnetron plasma has been investigated. The damage was characterized by Schottky barrier height measurements. The depths of the damaged layers were determined as a function of radio frequency (RF) power. It was found that the damaged layer at RF power of 2 kW (self-bias; 270 V) is about 12 nm, and that the damage depths correlate with the self-bias voltage, which is a measure of the energy of ions impinging on the Si surface during plasma exposure. Several methods for removal of the damaged layer have been examined; wet Si etching was found to be the most suitable one View full abstract»

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  • 3-D interconnection for ultra-dense multichip modules

    Page(s): 814 - 821
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    A three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection. The approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The process entails interconnecting the four lateral areas (sides) of the cube formed by stacking n chips (n=8-10) on top of one another. The chips are individually interconnected on a thin film identical to a TAB (tape automatic bonded) film by means of gold wires, prior to cubing. These chips are standard, off-the-shelf, bump-free devices. After passing electrical testing and burn-in, they are then glued on top of one another with the TAB film. After these n chip+film assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 μm from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross-sections may be interconnected in two different ways according to the number of chip layouts/outputs or the conductor pitch View full abstract»

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  • Large scale multilayer glass-ceramic substrate for supercomputer

    Page(s): 751 - 758
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    A large-scale multilayer glass-ceramic (MGC) substrate having a low dielectric constant (7.8) and a high flexural strength has been developed by a highly accurate green-sheet technology. The substrate has an area of 225 mm×225 mm and is 5.5 mm thick. A low electrical resistivity (3 μΩ-cm) can be realized by using a gold paste system is forming the conductors. The substrate can support high-density pattern processing due to the highly accurate process. Shrinkage can be controlled to 13.0%±0.3%, in spite of the large dimensions, by using shrinkage-control technology. The MGC substrate was used in the multilayer substrate (MLS) for supercomputer multichip packages. For the MLS, polyimide layers with signal line were formed on the MGC substrate. The new substrate has 78 layers, of which 13 are conductive layers, and 11540 I/O pins. The substrate houses up to 100 VLSI chips in a 225-mm square area, large scale MGC substrate properties, and supercomputer applications View full abstract»

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  • Effect of cooling mechanism and powering configurations on thermal impedances in an electronic enclosure

    Page(s): 967 - 974
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    An experimental investigation of the dependence of thermal impedance on a variety of typical design parameters including component arrangement, powering configuration, board placement, system orientation, and cooling mode is described. Some concepts of board and regional thermal impedances are introduced and the utility of these measures for performance comparison, data analysis, modeling, and design extrapolation is illustrated. A component-level energy balance is proposed to predict measured changes in peak component temperatures as a function of power level and location of neighboring components. Neighboring-component effects can increase effective junction to ambient thermal impedance by more than 25%. Measured heat transfer coefficients are compared to previously published values. The design issues of correcting for neighboring-component effects and utilizing the concept of regional thermal impedances are explored. A standardized portable database suitable for numerical model validation is described View full abstract»

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  • Low-loss fusion splicing of erbium-doped optical fibers for high performance fiber amplifiers

    Page(s): 811 - 813
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    An optimization process is described for reducing the fusion splice loss between Er-doped and standard single mode fibers, which differ significantly from each other in their physical and optical properties. As a result of this process, an average splice loss of 0.11 dB at 1300 nm in such fiber pairs has been achieved. The experimental splice loss data approached the theoretically predicted values. High-gain fiber amplifier experiments using the low-loss splicers obtained in the Er-doped and standard fiber combination are also discussed View full abstract»

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  • Thermal characteristics of single and multilayer high performance PQFP packages

    Page(s): 975 - 979
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    The thermal performance of previously introduced single-layer and multilayer plastic quad flat pack (PQFP) packages based on the work of D. Mallik, et al. (1989) is discussed. Using experimental and computational techniques, it is shown that significant reduction in the package thermal resistance can be achieved by using a multilayer lead frame structure for PQFP packages with medium and high lead counts. The measurement and analysis techniques are discussed. It is shown that in addition to enhancing the electrical performance, use of a multilayer lead frame design can provide a significant improvement in the thermal performance of PQFP packages. Thermal resistance in 132-lead PQFP is reduced by 38 and 43% with copper and Alloy 43 lead frames, respectively, under natural convection. A three-dimensional finite-element thermal model was constructed and correlated with the experimental data. Using this model, it is demonstrated that the contribution of the low thermal conductivity insulating adhesive tape to the overall thermal resistance is about 1°C/W View full abstract»

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  • Mechanism of electromigration in ceramic packages induced by chip-coating polyimide

    Page(s): 873 - 878
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    The mechanism of electromigration between the inner leads of large-scale integrated (LSI) chips in ceramic packages that are coated by thick polyimides to prevent alpha-particle-induced soft errors is discussed. Short-circuit failures between neighboring inner leads in the packages were monitored in the final test after burn-in of LSI devices. The shorting paths between the leads were observed by an optical microscope and scanning electron microscope (SEM). It was found that the path was produced by a deposit between the inner leads. The deposit was found to be composed of electromigration nickel from the inner lead. Also, n-methyl-pyrrolidone (NMP) and water were found in the package by gas analysis. A possible short-circuiting mechanism is discussed View full abstract»

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  • Low dielectric material for multilayer printed wiring boards

    Page(s): 1115 - 1120
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    A low-dielectric material called maleimide styryl (MS) resin is discussed. It was developed by reacting styryl prepolymer with ether-type bismaleimide. Both the styryl prepolymer and the ether-type bismaleimide are compounds based on the relationship between the chemical structure and dielectric constant. Since MS resin has good processabilities, its prepregs and copper-clad laminates can be made under the conventional processing conditions of epoxy and polyimide laminates. The MS laminates are characterized by their excellent heat resistance, similar to that of polyimide laminates, and low moisture absorption, similar to that of epoxy laminates. The laminates consist of the MS resin and several reinforcements having low dielectric constants ranging from 3.3 to 3.7. A high-density multilayer printed board with 62 printed wiring layers was made using the laminates; its capabilities are discussed View full abstract»

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Aims & Scope

This Transaction ceased production in 1993. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope