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Solid-State Circuits, IEEE Journal of

Issue 5 • Date Oct 1990

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Displaying Results 1 - 25 of 33
  • A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

    Publication Year: 1990 , Page(s): 1232 - 1238
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C View full abstract»

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  • Novel design for testability schemes for CMOS ICs

    Publication Year: 1990 , Page(s): 1239 - 1246
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations View full abstract»

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  • A 15-ns 4-Mb CMOS SRAM

    Publication Year: 1990 , Page(s): 1063 - 1067
    Cited by:  Papers (9)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (×4 or ×1) bit organization has been developed based on a 0.55-μm triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55-μm CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either ×4 or ×1 can be selected purely electrically, and does not require any pin connection procedure View full abstract»

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  • A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

    Publication Year: 1990 , Page(s): 1068 - 1074
    Cited by:  Papers (25)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    A 20 ns 4-Mb CMOS SRAM operating at a single supply voltage of 3.3 V is described. The fast access time has been achieved by a newly proposed word-decoding architecture and a high-speed sense amplifier combined with the address transition detection (ATD) technique. The RAM has the fast address mode, which achieves quicker than 10-ns access, and the 16-b parallel test mode for the reduction of test time. A 0.6-μm process technology featuring quadruple-polysilicon and double-metal wiring is adopted to integrate more than 16 million transistors in a 8.35-mm×18.0-mm die View full abstract»

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  • A static RAM chip with on-chip error correction

    Publication Year: 1990 , Page(s): 1290 - 1294
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip) is described. The linear sum code (LSC)-based ECCRAM is capable of correcting error at any addressed bit as long as there are no more than two errors in the 17 b (the logical row and column) associated with that addressed bit. Test results show that significantly larger error-recovery capability is present in the ECCRAM chip compared to memory chips without error correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with a 3-μm feature size View full abstract»

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  • Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

    Publication Year: 1990 , Page(s): 1217 - 1225
    Cited by:  Papers (95)  |  Patents (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block View full abstract»

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  • A CMOS mainframe processor with 0.5-μm channel length

    Publication Year: 1990 , Page(s): 1166 - 1177
    Cited by:  Papers (4)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability View full abstract»

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  • An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

    Publication Year: 1990 , Page(s): 1147 - 1152
    Cited by:  Papers (7)  |  Patents (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor View full abstract»

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  • A 23-ns 1-Mb BiCMOS DRAM

    Publication Year: 1990 , Page(s): 1102 - 1111
    Cited by:  Papers (31)  |  Patents (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm2, in spite of a 1.3-μm lithography level View full abstract»

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  • An improved latching pulse design for dynamic sense amplifiers

    Publication Year: 1990 , Page(s): 1294 - 1299
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    A generalized optimal latching pulse for dynamic sense-amplifier design has been derived. The model equations account for threshold-voltage imbalance bit-line capacitance imbalance, current-gain imbalance, gate capacitance and intra-bit-line capacitive coupling effect, channel-length modulation, source-body effect, and temperature sensitivity in a unified manner. Computer simulations of the analytical equations, including those effects, are presented. The analytical results provide physical insight into sensing speed and the sensitivity of optimized waveforms in terms of process imbalances, device model parameters, and circuit design variables. A design implementation for fast sense-amplifier operation is also presented to demonstrate the utility of the model equations for practical application View full abstract»

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  • An efficient and flexible architecture for high-density gate arrays

    Publication Year: 1990 , Page(s): 1153 - 1157
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    The authors describe an efficient and flexible HDGA (high-density gate array) architecture (or sea of transistors) with cells containing three common-gate wide and small transistors on which both logic and memory functions can be relatively densely mapped. The use of titanium-silicide straps for local interconnect (as an alternative to the third metal layer) is evaluated through different designs. The design and performance of an experimental chip in 0.8-μm CMOS technology are discussed. In a comparison of many different standard-cell and common-gate HDGA designs, the HDGA implementations showed equal performance at comparable or even smaller chip areas View full abstract»

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  • Analytic and iterative transit-time models for VLSI MOSFETs in strong inversion

    Publication Year: 1990 , Page(s): 1257 - 1267
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    Analytic and iterative transit-time models for both long-and short-channel MOSFETs are developed. The derivation is based on common compact IC drain-current models such as BSIM; thus, the short-channel expressions can account for effects such as velocity saturation, channel-length modulation, drain-induced barrier lowering, and two-dimensional charge sharing. The transit-time models are compared with estimates obtained from two-dimensional numerical simulation in order to see how closely simple analytic expressions will follow the more complicated numerical technique. For the long-channel case, traditional first-order analytic transit-time models show good agreement with the numerical results in the saturation region. At low drain bias, the importance of including gate-dependent surface scattering in the analytic mobility model is illustrated. The short-channel expressions also show good agreement at low to middle drain bias. A nonphysical result present at high electric fields which is due to the mobility expression commonly used in IC compact models to account for velocity saturation is identified. A new iterative transit-time model which avoids this problem is presented View full abstract»

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  • A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

    Publication Year: 1990 , Page(s): 1075 - 1081
    Cited by:  Papers (12)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm2 and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm2 View full abstract»

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  • A voltage reduction technique for battery-operated systems

    Publication Year: 1990 , Page(s): 1136 - 1140
    Cited by:  Papers (21)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    Two techniques for voltage reduction are presented, both of which can significantly reduce the power consumption of digital CMOS circuits. The fixed reduction of voltage is applicable to small systems with a low initial consumption, however, the optimum voltage is not reached and the correct operation of the circuit is not guaranteed. The self-adjusted reduction of voltage is adapted to bigger digital systems. The correct operation of the digital circuit is guaranteed, and the supply voltage is near the optimum for the speed requirements. This technique is more versatile, accurate, and reliable than the fixed one View full abstract»

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  • Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

    Publication Year: 1990 , Page(s): 1247 - 1256
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5-μm CMOS inverters with RC tree interconnection networks. An experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed-improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for a minimum delay. The four speed-improvement techniques use minimum-size repeaters and cascaded input drivers to reduce the interconnection delay. It is found that the required tapering factor in cascaded drivers is not the base of the natural logarithm, but a value in the range 4-8. Adding a small number of drivers/repeaters with large sizes reduces the interconnection delay more efficiently View full abstract»

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  • 8-ns CMOS 64 K×4 and 256 K×1 SRAMs

    Publication Year: 1990 , Page(s): 1047 - 1056
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    SRAMs (static random-access memory) with a 64 K×4 and 256 K×1 structure and with 8-ns access time have been developed on a 1.0-μm CMOS process. Circuits are designed with source-coupling techniques to achieve high speed with small signal swings, using only CMOS devices. A metal option permits selection of the 64 K×4 or 256 K×1 configuration. The same core architecture has also been used to generate ×8 and ×9 designs. An output-enable (OE) version achieves 3-ns response time. As system speeds have recently increased toward 100-MHz operation, the need for address transition detection (ATD) has diminished as a means for improving the SRAM speed/power ratio. This trend in SRAM design stems mainly from the fact that AC current becomes the most significant fraction of the total current. Accordingly, the design described here employs a purely static path through the entire SRAM, with no requirement of ATD at any point. The resulting DC current is countered with a combined strategy of array subdivision, small-signal techniques, and active preamplification at key points in the data path View full abstract»

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  • A 6.5-ns GaAs 20×20-b parallel multiplier with 67-ps gate delay

    Publication Year: 1990 , Page(s): 1226 - 1231
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4×4-b, to 6.48 ns (67 ps/ gate) for the 20×20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20×20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range View full abstract»

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  • A 5-ns 1-Mb ECL BiCMOS SRAM

    Publication Year: 1990 , Page(s): 1057 - 1062
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation View full abstract»

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  • A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM

    Publication Year: 1990 , Page(s): 1158 - 1165
    Cited by:  Papers (19)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI has been developed using a 0.8-μm triple-layer-Al, CMOS fabrication technology. A 13.02×12.51-mm2 chip contains a specially developed 160-kb content addressable memory (CAM) and cellular automation processor (CAP). A single DISP chip can store a maximum of 2048 words, and performs dictionary search in various search modes, including an approximate word search. The character input rate for the dictionary search operation is 33 million characters per second. The DISP typically consumes 800 mW at a supply voltage of 5 V. A high-speed, functional 50000 word dictionary search system can be built with 25 DISP chips arranged in parallel, to play an important role in natural language processing View full abstract»

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  • Pulse-density modulation technique in VLSI implementations of neural network algorithms

    Publication Year: 1990 , Page(s): 1277 - 1286
    Cited by:  Papers (46)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    New implementations of fully connected neural network architecture are explored, and some efficient implementations based on the pulse-density modulation technique are presented. These VLSI circuits are fully programmable, thereby usable in many applications. The architecture is implemented by using two different approaches: analog implementation with switched-capacitor structures and fully digital implementation. The approaches are also compared from the VLSI point of view. The advantage of the switched-capacitor implementation is the small area of a synapse, thus relatively large networks can be implemented. The architecture of the network is also regular, modular, and easy to expand. For the same complexity of network architecture, the digital implementation requires 30% more silicon area, which can be considered quite insignificant. The advantage of the fully digital implementation is good expandability to larger networks. In addition, single circuits can be joined together to form very large networks View full abstract»

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  • A CMOS RISC CPU designed for sustained high performance on large applications

    Publication Year: 1990 , Page(s): 1190 - 1198
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0-μm CMOS process that utilizes three-level metal and 480000 transistors on a 14×14-mm die View full abstract»

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  • A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

    Publication Year: 1990 , Page(s): 1199 - 1206
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit View full abstract»

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  • Level-shifted 0.5-μm BiCMOS circuits

    Publication Year: 1990 , Page(s): 1214 - 1216
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A circuit concept, level shifting, is presented for scaled BiCMOS circuits. A full-swing, ground-level-shifted (FS-GLS) BiCMOS circuit has shown approximately 1.6× speed improvement over a conventional partial-swing BiCMOS circuit, and a 4× better driving capability over a CMOS circuit at 3.3 V. With a high-performance p-n-p device, simulations show that the level-shifted complementary BiCMOS can provide further speed leverage over the BiCMOS circuit with n-p-n only View full abstract»

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  • Predicted propagation delay of Si/SiGe heterojunction bipolar ECL circuits

    Publication Year: 1990 , Page(s): 1268 - 1276
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    A comparison between the predicted propagation delays of ECL (emitter coupled logic) circuits composed of Si/SiGe heterojunction and silicon homojunction bipolar transistors is presented. Important transistor parameters such as the current gain, base transit time, base resistance, and emitter delay are calculated for the heterojunction transistor as a function of the Ge concentration in the SiGe base. This allows the important design tradeoffs for the heterojunction device to be identified. The calculations show that a Ge concentration of 12% is sufficient to allow the reversal of the usual emitter and base doping concentrations in a transistor with a base width of 0.02 μm. The resulting transistor has a gain of >50 and an emitter delay of <1 ps. A quasi-analytical expression is used to calculate the propagation delay of 1-μm ECL circuits incorporating the above transistor. A propagation delay of 15 ps is predicted for fully optimized Si/SiGe heterojunction circuits, compared with 29 ps for fully optimized silicon homojunction circuits. On scaling to geometries below 0.5 μm, a propagation delay of 10 ps is predicted for Si/SiGe heterojunction circuits View full abstract»

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  • The 68040 32-b monolithic processor

    Publication Year: 1990 , Page(s): 1178 - 1189
    Cited by:  Papers (9)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    A 32-b single-chip processor has been developed that is user object-code compatible with members of the 68000 processor family. The 14-4-mm×15.5-mm device contains over 1.2 million transistors and is fabricated with a double-layer-metal CMOS process. The processor integrates three major functional units: an integer processor: a floating-point processor; and a Harvard-style memory unit. Each major unit is described, and the implementation techniques that were employed and selected circuit issues that were confronted in the design are discussed View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan