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IEEE Journal of Solid-State Circuits

Issue 5 • Date Oct. 1972

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Displaying Results 1 - 25 of 27
  • [Front cover - October 1972]

    Publication Year: 1972, Page(s): f1
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    Freely Available from IEEE
  • [Inside front cover - October 1972]

    Publication Year: 1972, Page(s): f2
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    Freely Available from IEEE
  • Foreword: Special Issue on Semiconductor Memories and Digital Circuits

    Publication Year: 1972, Page(s): 325
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    Freely Available from IEEE
  • A surface-charge random-access memory system

    Publication Year: 1972, Page(s):330 - 335
    Cited by:  Papers (8)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    The authors present a surface-charge storage cell suitable for word-organized dynamic random-access memory and discuss its operation in a memory system. Experimental results and computer simulations of the readout process on a 4/spl times/8 array using this cell are given. A sensitive stable sense-and-refresh amplifier, suitable for use with this memory cell is also described. Simulations of a 409... View full abstract»

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  • A new complementary bipolar transistor structure

    Publication Year: 1972, Page(s):351 - 357
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complem... View full abstract»

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  • A large-scale integrated correlator

    Publication Year: 1972, Page(s):357 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (850 KB)

    A 64-bit parallel correlator is described using a large-scale integrated single-chip bipolar transistor construction. The circuit operates at 20 MHz and has an analog correlation output. The LSI structure uses the triple diffusion process, which produces both n-p-n and p-n-p transistors. Resistors are also diffused. A combination of soft saturated register circuits and nonsaturating gating circuit... View full abstract»

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  • Yield analysis of large integrated-circuit chips

    Publication Year: 1972, Page(s):389 - 395
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (818 KB)

    It has been experimentally observed that integrated-circuit yields decrease as their size increases and various attempts have been made to explain the variation. The authors analyze yield in terms of the geometrical factors involved in producing large chips from circular slices. It is shown that the qualitatively correct dependence of yield on area is obtained when a defect density that is higher ... View full abstract»

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  • A means of reducing custom LSI interconnection requirements

    Publication Year: 1972, Page(s):395 - 404
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1199 KB)

    Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective cir... View full abstract»

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  • Active bandpass filtering with bucket-brigade delay lines

    Publication Year: 1972, Page(s):421 - 425
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB)

    Bucket-brigade delay lines have been used to build a tunable active bandpass filter. Experimental results showing the dependence of center frequency and bandwidth on the delay-line clock frequency, and the dependence of the center frequency and the Q of the filter on internal gain parameters are presented. View full abstract»

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  • Transistor used as an adjustable bipolar low-level DC source

    Publication Year: 1972, Page(s):431 - 434
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    The use of a saturated transistor with a collector current opposite to the usual leads to a versatile, stable, and easily adjustable dc source with an EMF ranging from -10 to +10 mV and a low temperature drift. This source may be used to compensate the input offset voltage of a monolithic opamp whenever the impedance must be kept near zero or as low as 1 /spl Omega/. It can be built into an IC des... View full abstract»

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  • Comment on "Single-ended-input single-ended-output four-quadrant analog multiplier"

    Publication Year: 1972, Page(s): 434
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB)

    See abstr. B277 and C2113 of 1972. View full abstract»

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  • Contributors (October 1972)

    Publication Year: 1972, Page(s):435 - 440
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    Freely Available from IEEE
  • [Back inside cover]

    Publication Year: 1972, Page(s): b1
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  • DC-coupled low-power digit detector

    Publication Year: 1972, Page(s):418 - 421
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A monolithic integrated digit detector for a plated-wire memory system is described. It consists of a two-stage differential amplifier, a narrow-strobe gate, a preset gate, and a register (a set-reset flip-flop) that stores the detected signal during the time between the narrow-strobe pulse and the preset pulse. The device features high sensitivity of 1.3 mV and low-power dissipation of 100 mW. Th... View full abstract»

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  • Basewidth modulation and nonlinear β in CADA models

    Publication Year: 1972, Page(s):428 - 431
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A method is presented for modifying the expression for common-emitter gain in an Ebers-Moll model to include the effects of basewidth modulation and nonlinear β. The technique is one that most electrical engineers will find natural because the modified gain relationships are determined entirely from the collector characteristics of the device modeled. The modeling technique is applied to a me... View full abstract»

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  • Low-cost associative memory

    Publication Year: 1972, Page(s):364 - 369
    Cited by:  Papers (12)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    The authors describe the design of two high-density MOS associative memory cells. The first cell is suitable for data management applications, having three internal states including the DON'T CARE (mask) condition. The second cell is suitable for parallel processing applications and has the capability of selected bit writing. Both cells consume about 20 mil/SUP 2/ of silicon area, which allows the... View full abstract»

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  • Transient selection gates using breakdown

    Publication Year: 1972, Page(s):326 - 329
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    A new class of gates suitable for selection in memories is presented. The gate utilizes charge storage and avalanche breakdown to obtain a low power dissipation (~6×10/SUP -12/ J/selection, or ~60 μW/gate in a 10-MHz-repetition selection rate), more than an order of magnitude below that of conventional TTL gates. Only narrow (≳ 1 ns), nonoverlapping pulses are needed and external dc ... View full abstract»

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  • The field-effect modified transistor: a high-responsivity photosensor

    Publication Year: 1972, Page(s):411 - 417
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A new photosensing device that can be described as a field-effect modified bipolar transistor, has been developed. A novel technique of reducing the effective collector capacitance without reducing the total primary photocurrent provides for a decade improvement in responsivity for the FEM phototransistor operating in the charge-storage mode. Other applications of this device include a high noise-... View full abstract»

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  • IGFET/BIGFET decoder/driver with memory for LED displays

    Publication Year: 1972, Page(s):425 - 427
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The bipolar-IGFET structure has been utilized as the driver element in an integrated IGFET light-emitting diode decoder/driver with memory for seven-segment numeric displays. This combination of BIGFET output devices with high-yield high-packing-density IGFET logic provides the opportunity for economic gains from both lower power consumption and reduced silicon area requirements. The displays real... View full abstract»

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  • MNOS memory transistors in simple memory arrays

    Publication Year: 1972, Page(s):382 - 388
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    The basic properties of MNOS memory transistors as digital memory elements are reviewed. Optimization procedures for obtaining maximum memory retention are presented and possible arrangements of memory transistors in simple arrays and writing and reading procedures for such arrays are discussed. View full abstract»

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  • Shunt-feedback Schottky clamped logic gates

    Publication Year: 1972, Page(s):404 - 411
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well ... View full abstract»

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  • Electrically reprogrammable nonvolatile semiconductor memory

    Publication Year: 1972, Page(s):369 - 375
    Cited by:  Papers (21)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described. The fabrication data and the results of measurement on fabricated devices are shown. Analyses of the operation of the memory cell are done using conventional MOS transistors. The injection of current into silicon dioxide, its ratio to avalanche current, the WRITE sp... View full abstract»

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  • MAS-ROM-electrically reprogrammable ROM with decoder

    Publication Year: 1972, Page(s):375 - 381
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    The electrical characteristics of an MAS-ROM with on-the-chip X-Y matrix decoding and its reliabilities are evaluated. The MOS-ROM makes use of the so-called charge-storage phenomena in the gate insulator film and provides an electrical reprogrammable and nonvolatile integrated-circuit memory device in which one memory cell is composed only of an N-channel enhancement-type MAS transistor. The thre... View full abstract»

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  • Thermal incremental equivalent circuits of integrated circuit devices

    Publication Year: 1972, Page(s):427 - 428
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    A procedure of thermal stability design of integrated-circuit devices, based on the use of thermal incremental equivalent circuits, is described. These circuits may be derived by inspection from the dc equivalent circuit. They offer insight into the interdependence of various components in determining temperature variations and simplify the conventional analysis. View full abstract»

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  • Integrated injection logic: a new approach to LSI

    Publication Year: 1972, Page(s):346 - 351
    Cited by:  Papers (122)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 μm. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the c... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan