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Solid-State Circuits, IEEE Journal of

Issue 5 • Date Oct. 1972

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Displaying Results 1 - 25 of 27
  • [Front cover - October 1972]

    Page(s): f1
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    Freely Available from IEEE
  • [Inside front cover - October 1972]

    Page(s): f2
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    Freely Available from IEEE
  • Foreword: Special Issue on Semiconductor Memories and Digital Circuits

    Page(s): 325
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    Freely Available from IEEE
  • A surface-charge random-access memory system

    Page(s): 330 - 335
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    The authors present a surface-charge storage cell suitable for word-organized dynamic random-access memory and discuss its operation in a memory system. Experimental results and computer simulations of the readout process on a 4/spl times/8 array using this cell are given. A sensitive stable sense-and-refresh amplifier, suitable for use with this memory cell is also described. Simulations of a 4096-bit chip with a storage cell density of 2.5 mils/SUP 2//bit using this refresh amplifier predict a cycle time of 250 ns. View full abstract»

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  • A new complementary bipolar transistor structure

    Page(s): 351 - 357
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    A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process. View full abstract»

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  • A large-scale integrated correlator

    Page(s): 357 - 363
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    A 64-bit parallel correlator is described using a large-scale integrated single-chip bipolar transistor construction. The circuit operates at 20 MHz and has an analog correlation output. The LSI structure uses the triple diffusion process, which produces both n-p-n and p-n-p transistors. Resistors are also diffused. A combination of soft saturated register circuits and nonsaturating gating circuits produce a 25-pJ gate performance with device f/SUB t/ in the range 50-150 MHz. The logic form used is emitter-follower logic. This 5000 device, 220- by 230-mil chip, is a highly producible LSI function. View full abstract»

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  • Yield analysis of large integrated-circuit chips

    Page(s): 389 - 395
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    It has been experimentally observed that integrated-circuit yields decrease as their size increases and various attempts have been made to explain the variation. The authors analyze yield in terms of the geometrical factors involved in producing large chips from circular slices. It is shown that the qualitatively correct dependence of yield on area is obtained when a defect density that is higher near the outside of the slice is assumed. Results of computer program calculations of the maximum possible number of chips that can be obtained from a slice are given, assuming both random and nonrandom defect distributions. View full abstract»

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  • A means of reducing custom LSI interconnection requirements

    Page(s): 395 - 404
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    Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective circuits that naturally occur on such large circuit arrays, it has been necessary to customize each wafer's interconnection mask to its unique yield pattern. The authors examine in detail a means of using each mask set for perhaps several unique wafers, thus providing important custom routing and mask generation cost savings. In the case of pad relocation, only a single mask then comprises the entire custom mask set for several wafer arrays. View full abstract»

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  • Active bandpass filtering with bucket-brigade delay lines

    Page(s): 421 - 425
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    Bucket-brigade delay lines have been used to build a tunable active bandpass filter. Experimental results showing the dependence of center frequency and bandwidth on the delay-line clock frequency, and the dependence of the center frequency and the Q of the filter on internal gain parameters are presented. View full abstract»

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  • Transistor used as an adjustable bipolar low-level DC source

    Page(s): 431 - 434
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    The use of a saturated transistor with a collector current opposite to the usual leads to a versatile, stable, and easily adjustable dc source with an EMF ranging from -10 to +10 mV and a low temperature drift. This source may be used to compensate the input offset voltage of a monolithic opamp whenever the impedance must be kept near zero or as low as 1 /spl Omega/. It can be built into an IC design with only a single-pin control line. View full abstract»

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  • Contributors (October 1972)

    Page(s): 435 - 440
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    Freely Available from IEEE
  • [Back inside cover]

    Page(s): b1
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  • Electrically reprogrammable nonvolatile semiconductor memory

    Page(s): 369 - 375
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    Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described. The fabrication data and the results of measurement on fabricated devices are shown. Analyses of the operation of the memory cell are done using conventional MOS transistors. The injection of current into silicon dioxide, its ratio to avalanche current, the WRITE speed, the basic data for analog memory, and the drift of the characteristics are measured and discussed. View full abstract»

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  • DC-coupled low-power digit detector

    Page(s): 418 - 421
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    A monolithic integrated digit detector for a plated-wire memory system is described. It consists of a two-stage differential amplifier, a narrow-strobe gate, a preset gate, and a register (a set-reset flip-flop) that stores the detected signal during the time between the narrow-strobe pulse and the preset pulse. The device features high sensitivity of 1.3 mV and low-power dissipation of 100 mW. This high-sensitivity low-power digit detector is suitable for low-cost integration. View full abstract»

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  • Basewidth modulation and nonlinear β in CADA models

    Page(s): 428 - 431
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    A method is presented for modifying the expression for common-emitter gain in an Ebers-Moll model to include the effects of basewidth modulation and nonlinear β. The technique is one that most electrical engineers will find natural because the modified gain relationships are determined entirely from the collector characteristics of the device modeled. The modeling technique is applied to a medium-power silicon transistor; the measured collector characteristics used to generate the model are compared with collector characteristics computed from the resulting model. View full abstract»

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  • Merged-transistor logic (MTL)-a low-cost bipolar logic concept

    Page(s): 340 - 346
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    The authors describe a novel bipolar logic featuring a direct injection of minority carriers into the switching transistor. MTL is based on inverters having decoupled multicollector outputs for the logical combinations. The devices are self-isolated and no ohmic load resistors are required. This is a key to monolithic logic chips of very high functional density and low power dissipation. On experimental chips an excellent power-delay product of 0.35 pJ has been measured. These experiments show that a density of 100 gates/mm/SUP 2/ can be achieved with present manufacturing tolerances (minimum dimensions: 0.3-mil metal line width, 0.15-mil spacing, 0.2×0.2-mil/SUP 2/ contact holes). View full abstract»

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  • The field-effect modified transistor: a high-responsivity photosensor

    Page(s): 411 - 417
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    A new photosensing device that can be described as a field-effect modified bipolar transistor, has been developed. A novel technique of reducing the effective collector capacitance without reducing the total primary photocurrent provides for a decade improvement in responsivity for the FEM phototransistor operating in the charge-storage mode. Other applications of this device include a high noise-immunity inverter, a light intensity-to-frequency converter, and a simple semiconductor memory element. FEM transistors can be fabricated using the same processing schedule used for conventional bipolar transistors; no additional steps are required. View full abstract»

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  • MAS-ROM-electrically reprogrammable ROM with decoder

    Page(s): 375 - 381
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    The electrical characteristics of an MAS-ROM with on-the-chip X-Y matrix decoding and its reliabilities are evaluated. The MOS-ROM makes use of the so-called charge-storage phenomena in the gate insulator film and provides an electrical reprogrammable and nonvolatile integrated-circuit memory device in which one memory cell is composed only of an N-channel enhancement-type MAS transistor. The threshold voltage of the transistor is selectively increased by electron injection from the channel and decreased by the application of high negative voltage to the gate. The reliability test shows that the long-term decay has a logarithmic dependence on time with a slope of 0.7 V per decade of storage time under a gate voltage of +10 V at 150°C. View full abstract»

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  • Storage array and sense/refresh circuit for single-transistor memory cells

    Page(s): 336 - 340
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    For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 μm/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier). View full abstract»

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  • MNOS memory transistors in simple memory arrays

    Page(s): 382 - 388
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    The basic properties of MNOS memory transistors as digital memory elements are reviewed. Optimization procedures for obtaining maximum memory retention are presented and possible arrangements of memory transistors in simple arrays and writing and reading procedures for such arrays are discussed. View full abstract»

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  • Thermal incremental equivalent circuits of integrated circuit devices

    Page(s): 427 - 428
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    A procedure of thermal stability design of integrated-circuit devices, based on the use of thermal incremental equivalent circuits, is described. These circuits may be derived by inspection from the dc equivalent circuit. They offer insight into the interdependence of various components in determining temperature variations and simplify the conventional analysis. View full abstract»

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  • IGFET/BIGFET decoder/driver with memory for LED displays

    Page(s): 425 - 427
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    The bipolar-IGFET structure has been utilized as the driver element in an integrated IGFET light-emitting diode decoder/driver with memory for seven-segment numeric displays. This combination of BIGFET output devices with high-yield high-packing-density IGFET logic provides the opportunity for economic gains from both lower power consumption and reduced silicon area requirements. The displays realizable with this technological approach offer potential power savings of from 27 to 96 percent depending upon the application when compared to functionally equivalent all-bipolar circuits. View full abstract»

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  • Integrated injection logic: a new approach to LSI

    Page(s): 346 - 351
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    Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 μm. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L). View full abstract»

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  • Shunt-feedback Schottky clamped logic gates

    Page(s): 404 - 411
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    A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan