IEEE Journal of Solid-State Circuits

Issue 3 • June 1987

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Displaying Results 1 - 25 of 38
  • [Inside front cover - June 1987]

    Publication Year: 1987, Page(s): f2
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  • Table of contents (June 1987)

    Publication Year: 1987, Page(s):313 - 314
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  • Foreword (June 1987)

    Publication Year: 1987, Page(s): 315
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  • Best Paper Award

    Publication Year: 1987, Page(s): 316
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  • 5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

    Publication Year: 1987, Page(s):385 - 389
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (966 KB)

    A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double samp... View full abstract»

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  • Errata to "Analysis and Design Optimization of Domino CMOS Logic with Application to Standard Cells"

    Publication Year: 1987, Page(s): 496
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    First Page of the Article
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  • Patent abstracts (June 1987)

    Publication Year: 1987, Page(s):497 - 500
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  • [Back inside cover - June 1987]

    Publication Year: 1987, Page(s): b1
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  • Linearization of voltage-controlled oscillators using switched capacitor feedback

    Publication Year: 1987, Page(s):494 - 496
    Cited by:  Papers (18)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The voltage-frequency characteristics of any voltage-controlled oscillator can be linearized using a simple circuit containing a switched capacitor. The oscillation frequency becomes insensitive to power supply or temperature variations, and is determined only by the values of a capacitor, resistor, and the control voltage with respect to a reference voltage. View full abstract»

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  • Measurement and modeling of short-channel MOS transistor gate capacitances

    Publication Year: 1987, Page(s):464 - 472
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB)

    A flexible electrometer method for measuring the gate capacitances of small-geometry MOS transistors is described. This technique applies to standard test transistors requiring any on-chip circuitry. Subfemtofarad accuracy and high resolution (better than 0.1 fF) have been achieved. This technique permits flexibility with regard to choices of DC biases and test devices and provides a good means of... View full abstract»

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  • A versatile CMOS linear transconductor/square-law function

    Publication Year: 1987, Page(s):366 - 377
    Cited by:  Papers (189)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1832 KB)

    A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are... View full abstract»

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  • A single-chip linear-predictive-coding vocoder

    Publication Year: 1987, Page(s):479 - 487
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1664 KB)

    A NMOS vocoder IC, compatible with the LPC-10-2400-b/s speech coding standard, is described. The IC implements an adaptive linear predictive coding (LPC) spectral analyzer, a pitch decoder using Gold's algorithm, and a speech synthesizer. The algorithms, architecture, and circuit design methods have been clearly optimized to allow a single-chip implementation. View full abstract»

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  • A CMOS DRAM controller chip implementation

    Publication Year: 1987, Page(s):491 - 494
    Cited by:  Papers (1)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 μm twin-tub CMOS technology, nominal DRC devices operate at an internal clock rate of 36 MHz. High circuit speed was achieved by the use of clock-skew minimization techniques to limit clock signal variations to within 3.0 ns throughout the chip, and a modi... View full abstract»

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  • Very-low-drop voltage regulator with a fully complementary power process

    Publication Year: 1987, Page(s):447 - 450
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    A very-low-drop voltage regulator is presented that uses an isolated-collector power p-n-p transistor structure to achieve an input-output voltage drop of 0.4 V at 1 A. The device includes a circuit which prevents quiescent current peaks when the p-n-p is in saturation and a Zener-zap trimmed reference makes possible ±1% output voltage tolerance. View full abstract»

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  • Precision compressor gain controller in CMOS technology

    Publication Year: 1987, Page(s):442 - 445
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A precision gain-control compressor which makes use of a CMOS compatible lateral bipolar transistor is described. Two similar circuits are presented that enable raises to positive as well as negative powers. These circuits are specifically designed for use in CMOS hearing-aid systems. View full abstract»

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  • A CMOS stereo 16-bit D/A converter for digital audio

    Publication Year: 1987, Page(s):390 - 395
    Cited by:  Papers (79)  |  Patents (73)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampli... View full abstract»

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  • A four-state EEPROM using floating-gate memory cells

    Publication Year: 1987, Page(s):460 - 463
    Cited by:  Papers (24)  |  Patents (104)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An electrically erasable programmable read-only memory (EEPROM) is used in a novel way as a four-state memory by charging the floating gate to determined values. The memory cell and the complete programming and readout circuit are described. Retention characteristics are investigated and found to confirm a thermionic emission model. Retention time is estimated to be more than 22 years at 125°C... View full abstract»

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  • A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

    Publication Year: 1987, Page(s):357 - 365
    Cited by:  Papers (215)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1216 KB)

    The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transisto... View full abstract»

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  • A highly linear CMOS buffer amplifier

    Publication Year: 1987, Page(s):330 - 334
    Cited by:  Papers (76)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 Ω at 20 kHz. View full abstract»

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  • Influences on soft error rates in static RAMs

    Publication Year: 1987, Page(s):430 - 436
    Cited by:  Papers (28)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1216 KB)

    Alpha-particle-induced soft error rates (SERs) in RAMs were measured by exposing commercial chips, with lid and protective coating removed, to an Americium-241 alpha source. These measurements have shown that, under normal operating conditions, resistive load SRAMs can be as sensitive as DRAMs. Measurements of variations of SER with cycle time and supply voltage were in broad agreement with a mode... View full abstract»

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  • A CMOS potentiostat for amperometric chemical sensors

    Publication Year: 1987, Page(s):473 - 478
    Cited by:  Papers (86)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    A simple CMOS integrated potentiostatic control circuit is described. The circuit maintains a constant bias potential between the reference and working electrodes. Chemical concentration signals are converted amperometrically to an output voltage with a slope of approximately 60 mV/μA. Redox currents from 0.1 to 3.5 μA can be measured with a maximum nonlinearity of ±2% over this range... View full abstract»

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  • A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

    Publication Year: 1987, Page(s):378 - 384
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well a... View full abstract»

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  • Design considerations of dense bipolar PLA's

    Publication Year: 1987, Page(s):488 - 491
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    Technology issues and circuit choices are addressed and the tradeoffs between density and performance are discussed. It is concluded that device density is of key importance to the overall circuit design of a programmable logic array (PLA). A very dense PLA can be designed with its decoder implemented using merged transistor logic circuits and array crosspoints using butted-emitter transistor layo... View full abstract»

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  • New dynamic logic and memory circuit structures for BICMOS technologies

    Publication Year: 1987, Page(s):450 - 453
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    The basic structure is based on merging three devices in an area of a single MOS transistor. It uses an MOS capacitor and bipolar and JFET transistors for storage, writing, and sensing, respectively. These circuit structures have significantly smaller area and faster speed of operation compared to the conventional dynamic logic and memory circuits. In dynamic serial memory, the area of the circuit... View full abstract»

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  • Noise optimization of switched-capacitor biquads

    Publication Year: 1987, Page(s):445 - 447
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Minimization of the switch noise level in switched-capacitor biquads is discussed. An analytical optimization procedure permits the designer to explore the different parameters in an expert way. A 20-kHz notch filter shows its feasibility. The signal-to-noise ratio is 90 dB and the chip area 1.0 mm/SUP 2/. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com