IEEE Journal of Solid-State Circuits

Issue 6 • Dec. 1986

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Displaying Results 1 - 25 of 37
  • [Inside front cover - December 1986]

    Publication Year: 1986, Page(s): f2
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  • 1986 Index IEEE Journal of Solid-State Circuits Vol. SC-21

    Publication Year: 1986, Page(s):i1 - i16
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  • Table of contents (December 1986)

    Publication Year: 1986, Page(s):897 - 898
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  • Foreword (December 1986)

    Publication Year: 1986, Page(s):899 - 900
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  • Corrections to "An Elliptic Continuous-Time CMOS Filter with On-Chip Automatic Tuning"

    Publication Year: 1986, Page(s): 1122
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (192 KB)

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  • Errata to "Continuous-Time MOSFET-C Filters in VLSI"

    Publication Year: 1986, Page(s): 1122
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  • Patent abstracts (December 1986)

    Publication Year: 1986, Page(s):1123 - 1127
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  • [Back inside cover - December 1986]

    Publication Year: 1986, Page(s): b1
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  • Characterisation and modeling of mismatch in MOS transistors for precision analog design

    Publication Year: 1986, Page(s):1057 - 1066
    Cited by:  Papers (415)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1744 KB)

    A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are v... View full abstract»

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  • Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

    Publication Year: 1986, Page(s):1045 - 1056
    Cited by:  Papers (19)
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    An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 μW at 3.5 V... View full abstract»

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  • A 2-V amplitude-linear phase-locked loop

    Publication Year: 1986, Page(s):934 - 940
    Cited by:  Papers (3)  |  Patents (1)
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    An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-μm CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier... View full abstract»

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  • An implantable multielectrode array with on-chip signal processing

    Publication Year: 1986, Page(s):1035 - 1044
    Cited by:  Papers (188)  |  Patents (5)
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    This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-μm apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circu... View full abstract»

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  • Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages

    Publication Year: 1986, Page(s):1120 - 1122
    Cited by:  Papers (21)
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    A novel four-quadrant CMOS analog multiplier has been designed and integrated using linearized differential stages as basic building blocks. The multiplier offers high input resistance and linear input ranges of ±2.5 V for a supply voltage of ±5 V. A 3-dB bandwidth of at least 1.6 MHz is attainable for either input. View full abstract»

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  • Design procedures for differential cascode voltage switch circuits

    Publication Year: 1986, Page(s):1082 - 1087
    Cited by:  Papers (103)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (864 KB)

    Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful picto... View full abstract»

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  • Switched-capacitor high-Q bandpass filters for IF applications

    Publication Year: 1986, Page(s):924 - 933
    Cited by:  Papers (37)  |  Patents (6)
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    Experimental results for a sixth-order switched-capacitor bandpass filter with a selectivity Q of 55 at a center frequency of 3.1 MHz are presented. A simple noise analysis of active bandpass filters composed of coupled identical resonators is introduced to explain the dynamic range reduction in high-Q active filters resulting from loose high-Q couplings between resonators. Theoretical predictions... View full abstract»

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  • A 50-Mbit/s CMOS optical transmitter integrated circuit

    Publication Year: 1986, Page(s):901 - 908
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1456 KB)

    An integrated circuit for an optical transmitter has been designed in a standard digital 1.5-μm CMOS technology. This production chip features a 50-MHz digital data scrambler, a trimmable temperature-compensated output current of between 50 and 80 mA, and switching times of <2 ns. Asynchronous speeds of over 200 Mb/s have been achieved. The design objectives of this integrated circuit as wel... View full abstract»

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  • A quad CMOS single-supply op amp with rail-to-rail output swing

    Publication Year: 1986, Page(s):1026 - 1034
    Cited by:  Papers (103)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1672 KB)

    The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation f... View full abstract»

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  • Programmable switched-capacitor low-pass ladder filters

    Publication Year: 1986, Page(s):1109 - 1119
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1888 KB)

    Switched-capacitor filters with digitally programmable capacitor arrays (DPCAs) offer a solution to the diverse needs to the market for audio-frequency high-order low-pass filters. Cascading switched-capacitor biquads which contain binary or geometrically weighted DPCAs are not a viable way to produce precision high-order responses, because of the errors introduced by capacitance quantization. To ... View full abstract»

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  • An 8-bit high-speed CMOS A/D converter

    Publication Year: 1986, Page(s):976 - 982
    Cited by:  Papers (36)  |  Patents (4)
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    An 8-bit high-speed A/D converter has been developed in a 1.5-μm bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimi... View full abstract»

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  • A high-performance 1-Mbit dynamic RAM with a folded capacitor cell

    Publication Year: 1986, Page(s):1076 - 1081
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (992 KB)

    The DRAM was fabricated using buried oxide (BOX) isolation technology and a two-level aluminium metallization scheme. High-speed operation has been realized by a newly developed high-speed sensing system along with reduced word-line resistances, using double-level aluminium metallization. Low-power operation has been achieved by incorporating a partial activation scheme of memory cell arrays and r... View full abstract»

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  • A switching regulator and lightning protector for a subscriber line interface circuit

    Publication Year: 1986, Page(s):947 - 955
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1384 KB)

    Two monolithic ICs, a switching regulator and a crowbar protector circuit fabricated in a 90-V complementary bipolar technology are described. These devices enhance the performance of a basic subscriber-line interface circuit (SLIC) by extending the range to the customer so that 20-mA DC feed current can be supplied to a 2800-Ω loop without the need for a -72-V office battery. The power diss... View full abstract»

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  • A CMOS double-heterodyne FM receiver

    Publication Year: 1986, Page(s):916 - 923
    Cited by:  Papers (10)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1320 KB)

    Experimental results for a narrow-band, adjustment-free double-heterodyne CMOS FM receiver with a high-Q switched-capacitor IF filter centered at 3 MHz are presented. The integration covers all the filtering and demodulation circuits from radio-frequency circuits (50-100 MHz) to the audio output. An experimental prototype FM receiver exhibiting a 5-mV input sensitivity and a -30-dB quieting level ... View full abstract»

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  • A 12-bit successive-approximation-type ADC with digital error correction

    Publication Year: 1986, Page(s):1016 - 1025
    Cited by:  Papers (24)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1408 KB)

    A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D ... View full abstract»

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  • 4-GHz band GaAs monolithic limiting amplifier

    Publication Year: 1986, Page(s):1103 - 1108
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (976 KB)

    An amplifier is described for use in the clock regeneration circuit for a gigabit optical transmission system. A phase-shift deviation of >5%° over the input dynamic range from -10 to 4 dBm at 1.8 GHz has been achieved. Experimental and simulation results are reported. To predict the performance of the limiting amplifier accurately, the JFET model in SPICE2 has been improved. View full abstract»

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  • A flat-panel display control IC with 150-V drivers

    Publication Year: 1986, Page(s):971 - 975
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (888 KB)

    A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resi... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com