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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Aug. 1986

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Displaying Results 1 - 22 of 22
  • [Inside front cover - August 1986]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1986)

    Page(s): 497
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    Freely Available from IEEE
  • Editor's Note (August 1986)

    Page(s): 499
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    Freely Available from IEEE
  • Best Paper Award

    Page(s): 500
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    Freely Available from IEEE
  • Patent abstracts (August 1986)

    Page(s): 592 - 598
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    Freely Available from IEEE
  • [Back inside cover - August 1986]

    Page(s): b1
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    Freely Available from IEEE
  • A wide-band low-noise monolithic transimpedance amplifier

    Page(s): 530 - 533
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    A transimpedance amplifier with nominal 200-MHz bandwidth, 6.6-kΩ gain, and 33-nA RMS-equivalent input noise current is described. The circuit is realized in silicon-bipolar-monolithic technology and functions with source capacitances ranging from zero to several picofarads. View full abstract»

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  • Optimization of the peaking current source

    Page(s): 587 - 590
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    An integrated-current reference is presented which is extremely simple but can be designed for enhanced supply voltage independence or temperature independence. The conditions for optimum circuit biasing are developed and presented in a way to enable the circuit designer to optimize the circuit for supply voltage independence, temperature independence, or both under a certain condition. The circuit is simulated using SPICE and experimental data is taken from an operating prototype. This circuit provides a reasonably stable current reference with very little penalty in the circuit layout area over a simple mirror-type current source which has no regulation capability. View full abstract»

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  • Interval estimates for yield modeling

    Page(s): 590 - 591
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    Follows statistical convention by calling estimates point estimates. Defect density is a random phenomenon; thus a function of defect density, namely yield, will also be a random variable. An analysis is proposed of the yield model that allows calculation of interval bounds for yield, based on flexible defect models. An examination is also made of the interval estimates for yield from an individual wafer, and the confidence intervals for average yield for a given type of wafer. View full abstract»

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  • Latched domino CMOS logic

    Page(s): 514 - 522
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    A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic. View full abstract»

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  • A 1-Mb/s IR LED array driver for office wireless communication

    Page(s): 582 - 584
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    The design of the 1-Mbit/s driver for IR LED arrays enables a wireless IR link to accommodate several voice and data users. With the coming availability of new and economical IR LED devices and with special optical filtering it is estimated that IR LED switching rates will be approaching the 5-Mb/s range. An IR wireless link in an office would thus be enabled to handle video signals. View full abstract»

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  • Intermodulation in high-frequency bipolar transistor integrated-circuit mixers

    Page(s): 534 - 537
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    Intermodulation in bipolar-transistor double-balanced mixers at high frequencies is analyzed theoretically and by computer simulation. The dependence of the distortion on a relatively few normalized parameters is illustrated. Computed results are compared with measurements on a monolithic quad mixer. View full abstract»

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  • Reference refreshing cyclic analog-to-digital and digital-to-analog converters

    Page(s): 544 - 554
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    A method of cyclic analog-to-digital (A/D) and digital-to-analog (D/A) conversion using switched-capacitor techniques is described. By periodically modifying the reference voltage to compensate for the nonideal signal-transfer-loop gain, it is possible in principle to build A/D and D/A converters whose linearity is independent of component ratios and that occupy only a small die area. These converters require two moderate-gain MOS operational amplifiers, one comparator, and a few capacitors. A test chip for A/D conversion was built and evaluated. The test data show that the A/D performs as a monotonic 13-bit converter with maximum 1-LSB differential and 2-LSB integral nonlinearity. View full abstract»

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  • A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS

    Page(s): 505 - 513
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    A design is presented for an 8-bit×8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-μm CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated. View full abstract»

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  • A 0.85-ns 1-kbit ECL RAM

    Page(s): 501 - 504
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    A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-μm design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 μm and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 μm in the first layer and 6 μm in the second one. The chip size is 2.5×2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems. View full abstract»

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  • A GaAs 8×8-bit multiplier/accumulator using JFET DCFL

    Page(s): 523 - 529
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    A description is given of a GaAs JFET LSI circuit containing approximately 1800 gates. The LSI circuit is composed of an 8×8-bit parallel multiplier and a 20-bit accumulator, and uses direct-coupled FET logic (DCFL) circuitry. Fully functional 8×8-bit multipliers have been fabricated and have displayed a multiplication time of 6.0 ns with a power dissipation of 876 mW, operating at a supply voltage of 1.46 V. The 20-bit accumulators have also shown complete operation at a supply voltage of 1.3 V. This LSI circuit is designed to operate in a pipelined fashion using a single clock. The design of the multiplier and the accumulator, the fabrication technology, and the performance of the complete chip are also discussed. View full abstract»

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  • A full adder using junction charge-coupled logic

    Page(s): 584 - 587
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    A full adder that is based on three-dimensional charge transport in junction charge-coupled devices (JCCDs) is presented. The basic current uses little chip area and is operated by a three-phase clock. No DC voltages are required for logic operation. The SUM and CARRY signals are calculated within one clock cycle. The concept of this full adder is suited to application in systolic arrays. View full abstract»

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  • A 5-mA 1-GHz GaAs dual-modulus prescalar IC

    Page(s): 538 - 543
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    A 1-GHz GaAs dual-modulus divide-by-128/129 prescalar IC with current drain of only 5 mA has been developed. Its current drain is one-sixth that of commercially available Si bipolar ICs used in 800-MHz band mobile radio systems. Five-level series gate low-power source-coupled FET logic (LSCFL) and the 0.50-μm gate buried P-layer SAINT (BP-SAINT) process technology have been used to achieve this small current drain together with high-speed operation. A high-speed divide-by-4/5 modulus divider (3.1 GHz, 13 mA) and divide-by-32 divider (6.1 GHz, 19 mA) has also been designed and fabricated. These prescalars are suitable for use as synthesizers in mobile communication systems. View full abstract»

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  • Compensation of bipolar monolithic circuits using the parasitic capacitance of diffused resistors

    Page(s): 568 - 574
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    A method of compensating bipolar integrated circuits which uses the parasitic capacitance of diffused resistors is studied. The advantages over other methods are: compatibility with the standard bipolar fabrication process, ease of implementation, and the possibility of controlling the overall bandwidth of an amplifier through adjustment of the bias of a resistor (for variable bandwidth applications or for compensation of process variations). The main drawback is the large size required. The sensitivity to process-parameter variations of the resulting compensation is shown to be comparable to that achieved with a MOS or N/SUP +/P capacitor. The MOS compensation is more stable with temperature variations. The diffused resistor models are shown to yield accurate results as long as a sufficient number of lumped sections are used when large area resistors are considered. View full abstract»

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  • Class E tuned power amplifier with nonsinusoidal output voltage

    Page(s): 575 - 581
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    An analysis is presented of the amplifier for a limiting case when the load network does not contain a series-resonant output circuit and the output voltage is non-sinusoidal. For optimum operation with any switch-duty ratio, the author has determined the current and voltage waveforms, the collector current and collector-emitter peak values, the output power, the power-output capability, and the load-network component values. The spectrum of the output voltage is given for a switch-duty ratio of 0.25, 0.5, and 0.75. Close-approximation equations are given for transistor power losses and collector efficiency. The experimental and theoretical results are in very good agreement. The measured collector efficiency is 95%. The circuit has practical applications, e.g., in high-efficiency switching-mode DC-to-DC converters used in DC power supplies for microcomputers or communication equipment. View full abstract»

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  • An analysis of fixed pattern noise for MOS-CCD type image sensors under quasi-stationary conditions

    Page(s): 555 - 560
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    A theoretical explanation for fixed pattern noise (FPN) is given for the MOS-CCD image sensor with the use of external bias charge. The FPN is ascribed to the fluctuation of the bias charge which is returned from the coupler between the vertical transport line and the horizontal CCD (H-CCD) shift register. It is shown that the FPN is eliminated below -60 dB with respect to the maximum output signal in the case of vertical transfer efficiency of 97% or more. View full abstract»

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  • A new bipolar reference current source

    Page(s): 561 - 567
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    A high-quality bipolar reference current source based on the bandgap of silicon is described that is independent of supply voltage and temperature variations. The circuit only uses identical n-p-n transistors processed in a conventional bipolar process. The circuit contains only a small number of components and needs no starting circuit. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan