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IEEE Journal of Solid-State Circuits

Issue 3 • Date June 1985

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Displaying Results 1 - 25 of 30
  • [Inside front cover - June 1985]

    Publication Year: 1985, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1985)

    Publication Year: 1985, Page(s):653 - 654
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    Freely Available from IEEE
  • Foreword (June 1985)

    Publication Year: 1985, Page(s):655 - 656
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    Freely Available from IEEE
  • A High-Resolution Capacitance-to-Frequency Converter

    Publication Year: 1985, Page(s):666 - 670
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB)

    This paper describes an integrated sampled-data sinusoidal oscillator with AGC amplitude stabilization, the frequency of which is proportional to an external low value capacitor (2-20 pF). The circuit, based on a switched-capacitor two-integrator loop, is insensitive to stray capacitances between sensing nodes and ground and features high resolution (16 bits) and excellent linearity (better than 0... View full abstract»

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  • A Receiver IC for a 1 + 1 Digital Subscriber Loop

    Publication Year: 1985, Page(s):671 - 678
    Cited by:  Papers (2)  |  Patents (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1011 KB)

    A receiver IC for a 1 + 1 digital transmission system is presented. It includes all the functions necessary for data recovery (high-pass filtering, automatic gain control (AGC), clock extraction, decision circuitry) and for supplying the control code to a separately integrated echo canceller. A total switched-capacitor (SC) approach with digital control is used and a complete description of the re... View full abstract»

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  • A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

    Publication Year: 1985, Page(s):679 - 687
    Cited by:  Papers (18)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (901 KB)

    A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLI... View full abstract»

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  • A High-Dynamic-Range Front End for an Upconversion Car-Radio Receiver

    Publication Year: 1985, Page(s):688 - 696
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1003 KB)

    A monolithically integrated high-performance front end for an AM radio receiver is presented. Medium- and long-wave reception without any tuned-circuit alignments or band switches is made possible by using an intermediate frequency of 10.7 MHz, well above the maximum frequency to be received. Image- and oscillator-harmonics-related spurious responses are rejected by a simple low-pass filter. The u... View full abstract»

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  • An Integrated IF Amplifier and Detector for an A.M. Upconversion Radio

    Publication Year: 1985, Page(s):697 - 702
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    This paper presents a monolithically integrated IF amplifier and envelope detector for an AM upconversion car-radio receiver. This receiver is intended for the reception of the long-wave and medium-wave frequency bands and uses an intermediate frequency of 10.7 MHz. Specific requirements resulting from the upconversion concept will be illustrated and the basic considerations for maximization of th... View full abstract»

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  • A Multiplexing/Demultiplexing Transceiver for 565-Mbit/s Fiber-Optic Links

    Publication Year: 1985, Page(s):708 - 714
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1126 KB)

    A high-performance silicon bipolar integrated circuit used in a 565-Mbit/s multiplex and optical-fiber transmission system will be described. The paper includes a functional description of the coder/decoder together with details of circuit design and layout techniques used to realize this demanding performance requirement. Measured results are presented which confirm the computer predicted perform... View full abstract»

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  • A Novel JCMOS Dynamic RAM Cell for VLSI Memories

    Publication Year: 1985, Page(s):715 - 723
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1315 KB)

    A high-density dynamic memory cell using the CMOS technology (JCMOS cell) is described. The cell is based on merging three different devices and occupies an area of a single MOS transistor. The cell consists of an enhancement surface MOSFET, a JFET, and a bipolar transistor. The data is stored on the MOS capacitor, sensed by the JFET, and written into the cell using the bipolar transistor. The cel... View full abstract»

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  • A Full Custom Integrated Circuit for Document Analysis Systems

    Publication Year: 1985, Page(s):730 - 740
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1287 KB)

    This paper describes the architecture and design methodology used to produce a new custom IC intended for automatic document analysis. The circuit implements the entire operative part of a dedicated microprogrammed processor for the next generation of page readers which include items such as Optical Character Recognition (OCR) and different codings for graphics and images. The chip provides a wide... View full abstract»

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  • A Design Style for VLSI CMOS

    Publication Year: 1985, Page(s):741 - 745
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1098 KB)

    CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and... View full abstract»

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  • A CMOS Design Strategy for Bit-Serial Signal Processing

    Publication Year: 1985, Page(s):746 - 753
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    We present a summary of the features and successes of a Silicon Compiler (FIRST) for LSI nMOS bit-serial signal processors. A replacement cell library of CMOS operators has been designed for the compilation of true VLSI bit-serial signal processors. The cell library is implemented in 2.5-/spl mu/m buIk CMOS technology, and maintains a consistent performance of 20 MHz. We describe the design philos... View full abstract»

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  • A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

    Publication Year: 1985, Page(s):754 - 760
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1249 KB)

    In this paper a 2-/spl mu/m CMOS, microprogrammable Signal Processor Core (SPC) is described,intended as the number crunching unit in single-chip general purpose digital signal processors. This core contains a 16 X 16 bit paralleI multiplier, a 40-bit multiprecision accumulator, a 40--32-bit extractor, an overflow detection unit, a format adjuster, and a three-port register file for local storage ... View full abstract»

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  • A CMOS 8-Bit High-Speed A/D Converter IC

    Publication Year: 1985, Page(s):775 - 779
    Cited by:  Papers (100)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (645 KB)

    A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to t... View full abstract»

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  • A 6-Bit/200-MHz Full Nyquist A/D Converter

    Publication Year: 1985, Page(s):780 - 786
    Cited by:  Papers (40)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    This paper deals with the development of an extremely fast 6-bit flash A/D converter. To gain insight into the nature of speed limitations, the effects arising from operation at very high sampling rates have been investigated. This led to the implementation of an optimized double-stage comparator circuit. The chip has been fabricated in a fast standard oxide isolated bipolar process. At a sampling... View full abstract»

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  • A Hard Disk Channel Processor

    Publication Year: 1985, Page(s):787 - 792
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A new hard disk controller (HDQ) LSI for 16/32-bit personal computers has been developed. The key feature of the controller is its on-chip DMA capability. The LSI operates as a channel processor based upon a Channel Control Word (CCW) scheme as well as a hard disk controller. Over 1.75-Mbyte/s disk data speed and over 6.6-Mbyte/s host bus data speed were obtained simultaneously. View full abstract»

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  • 350-V Display Driver Chip

    Publication Year: 1985, Page(s):793 - 798
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (682 KB)

    This paper describes a chip which implements 30 tri-state 350-V display drivers in a high-voltage MOS (HVMOS) technology using a dielectrically isolated substrate. Low-voltage contol logic is implemented on the same die, for data handling and input-output facilities. The device has been developed as a custom designed chip for Tape Automated Bonding (TAB) on a large glass substrate and is an import... View full abstract»

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  • A Micropower CMOS-Instrumentation Amplifier

    Publication Year: 1985, Page(s):805 - 807
    Cited by:  Papers (81)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (385 KB)

    A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-zero technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4-/spl mu/m double poly process has an offset (/spl tau/) of 370 /spl mu/V, an rms input referred integrated noise (0.5 -f/sub c//2) of 79 /spl mu/V, and consumes onl... View full abstract»

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  • A Design Strategy in CMOS for Microprocessors and Its Application to the Intel 80C48

    Publication Year: 1985, Page(s):807 - 809
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The main purpose in redesigning the 8048 Intel Microcomputer in CMOS technology is to test our tool's efficiency and to evaluate our design methodology, called CAPRI [1], which researches a good factor of regularity. This paper presents a method of implementing microprocessor circuitry in CMOS which uses an ordered stucture of the layout. It allows the designer to work, with a symbolism, on a grid... View full abstract»

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  • Low-voltage peaking complementary current generator

    Publication Year: 1985, Page(s):816 - 818
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    An improved peaking complementary current generator with accompanying automatic start-up circuitry is analyzed. It operates down to a supply voltage of 1 V and has excellent supply rail insensitivity. View full abstract»

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  • [Back inside cover - June 1985]

    Publication Year: 1985, Page(s): b1
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    Freely Available from IEEE
  • Modeling of a Dual-Drain NMOS Magnetic-Field Sensor

    Publication Year: 1985, Page(s):819 - 821
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    We present numerical results for the potential, current, and surface charge distributions as well as the sensitivity of a magnetic-field-sensitive split-drain n-channel MOSFET's operating in the linear region. We also present a suitable circuit configuration that incorporates this device and calculate the overall sensitivity of the resulting magnetic-field-sensitive circuit. Optimization of the de... View full abstract»

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  • TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout

    Publication Year: 1985, Page(s):799 - 804
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    TOPOLOGIZER is an expert system for the design of CMOS cells. TOPOLOGIZER uses heuristics (rules) specified by an expert designer to produce a custom-fit symbolic leaf-cell from a transistor connection description and a description of the environment in which the cell will reside. A symbolic layout system converts the symbolic description to a mask level description. View full abstract»

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  • The Design of High-Performance Analog Circuits on Digital CMOS Chips

    Publication Year: 1985, Page(s):657 - 665
    Cited by:  Papers (181)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com