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# IEEE Journal of Solid-State Circuits

## Filter Results

Displaying Results 1 - 25 of 33
• ### [Inside front cover - April 1985]

Publication Year: 1985, Page(s): f2
| PDF (155 KB)

Publication Year: 1985, Page(s):465 - 466
| PDF (165 KB)
• ### Foreword (April 1985)

Publication Year: 1985, Page(s):467 - 468
| PDF (310 KB)
• ### Advanced CMOS gate array architecture combining gate isolation' and programmable routing channels

Publication Year: 1985, Page(s):469 - 480
Cited by:  Papers (8)  |  Patents (21)
| | PDF (2201 KB)

A description is given of a novel CMOS gate array architecture for LSI/VLSI complexity. The new structure is based on the gate isolation' technique for logic implementation, in addition to the programmability of the amount of routing channels. This concept uses double-level metal with the first contact level programmable for the circuit customization. The gate array has been designed in a 3-/spl ... View full abstract»

• ### A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits

Publication Year: 1985, Page(s):481 - 488
Cited by:  Papers (2)  |  Patents (1)
| | PDF (1214 KB)

Edge contact transistors are widely used in basic cells of gate-array circuits and custom designed circuits. The role of sheet and contact in affecting the performance of these transistors is investigated. A two-dimensional model has been developed to calculate the transistor's effective series resistance at various bias conditions. Very good correlation between the model and experiments has been ... View full abstract»

• ### An isolated vertical n-p-n transistor in an n-well CMOS process

Publication Year: 1985, Page(s):489 - 494
Cited by:  Papers (3)  |  Patents (1)
| | PDF (1008 KB)

Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the... View full abstract»

• ### An integrated approach for hierarchical verification of VLSI mask artwork

Publication Year: 1985, Page(s):501 - 509
Cited by:  Papers (3)  |  Patents (3)
| | PDF (1342 KB)

An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design method... View full abstract»

• ### The TimberWolf placement and routing package

Publication Year: 1985, Page(s):510 - 522
Cited by:  Papers (267)  |  Patents (17)
| | PDF (2696 KB)

TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing l... View full abstract»

• ### Analysis and design optimization of domino CMOS logic with application to standard cells

Publication Year: 1985, Page(s):523 - 530
Cited by:  Papers (17)  |  Patents (5)
| | PDF (1212 KB)

The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implem... View full abstract»

• ### A 16 bitx16 bit pipelined multiplier macrocell

Publication Year: 1985, Page(s):542 - 547
Cited by:  Papers (21)  |  Patents (3)
| | PDF (1073 KB)

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfigur... View full abstract»

• ### A methodology for the fast and testable implementation of state diagram specifications [logic design]

Publication Year: 1985, Page(s):548 - 554
Cited by:  Papers (5)
| | PDF (923 KB)

A methodology is presented for the hierarchical structured design of state diagram specifications. It is based on a set of restrictions on the composition of the hierarchy that allows a design to be proven correct by construction. Furthermore, silicon primitives are introduced that permit a direct mapping of asynchronous and synchronous state diagrams. Special attention is paid to the use of scanp... View full abstract»

• ### An analog CMOS autopilot

Publication Year: 1985, Page(s):571 - 578
Cited by:  Patents (1)
| | PDF (1185 KB)

Results are presented of an analog LSI CMOS missile autopilot. The autopilot is a two-chip set which requires a total area of 210000 sq miles and consumes 700 mW of power. The set is fabricated in a double-poly p-well silicon-gate technology. The chips perform a wide array of analog functions, including precision filtering, full-wave demodulation, digital-to-analog conversion, limiting, pulsewidth... View full abstract»

• ### A custom data conversion subsystem for personal computers

Publication Year: 1985, Page(s):579 - 585
Cited by:  Patents (2)
| | PDF (1015 KB)

A `full custom' data conversion integrated circuit is described. it is used in a personal computer as an interface to the cassette recorder and the audio sound channel, and interfaces the joysticks to the computer. The chip contains a six-bit digital-to-analog converter (DAC), a three-channel multiplexer, a four-channel operational amplifier, and a comparator. The IC's unique features include the ... View full abstract»

• ### A generalized layout rule generator

Publication Year: 1985, Page(s):589 - 591
Cited by:  Papers (2)
| | PDF (480 KB)

As VLSI fabrication processes and systems become more complex, the number of layout rules required increases dramatically. A program is described that automatically creates and evaluates layout rules. The layout rules for a submicrometer CMOS process are generated and the variation of the density of a CMOS static RAM cell with process changes is illustrated. View full abstract»

• ### A 256K HCMOS ROM using a four-state cell approach

Publication Year: 1985, Page(s):598 - 602
Cited by:  Papers (8)  |  Patents (24)
| | PDF (743 KB)

A 256K HCMOS ROM design is discussed using a geometry-variable four-state cell for high packing density. Design, area, and process margin comparisons are made to other cell approaches. The architecture of the chip is shown and device performance is summarized. The 32K/spl times/8-bit ROM has typical access times of 200 ns with 11 mA of active current at 1000-ns cycle times and typical standby curr... View full abstract»

• ### An EEPROM for microprocessors and custom logic

Publication Year: 1985, Page(s):603 - 608
Cited by:  Papers (7)  |  Patents (21)
| | PDF (1174 KB)

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/. View full abstract»

• ### A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units

Publication Year: 1985, Page(s):617 - 622
Cited by:  Papers (6)
| | PDF (1135 KB)

A single-chip FM modulator/demodulator (modem) based LSI for the 800-MHz band land mobile radio unit has been developed. This LSI contains both digital and analog function blocks. The digital function block consists of high-speed digital PLL circuits such as a dual modulus prescaler, a programmable counter, and a phase frequency comparator for a 145 MHz direct FM modulator. The analog one consists... View full abstract»

• ### An integrated six-path wave-SC filter

Publication Year: 1985, Page(s):632 - 640
Cited by:  Papers (12)
| | PDF (1316 KB)

Experimental results of a switched capacitor (SC) N-path filter integrated in a CMOS Si-gate technology are reported, with N=6. The circuit is based on the theory of wave-flow networks and uses only fully stray-eliminating (usually referred to as stray-insensitive) SC amplifier and integrator circuits. The two main drawbacks of N-path filters, i.e. unwanted mirror frequencies due to path mismatch ... View full abstract»

• ### A switched capacitor oscillator with precision amplitude control and guaranteed start-up

Publication Year: 1985, Page(s):641 - 647
Cited by:  Papers (31)
| | PDF (970 KB)

A description is given of the design and performance characteristics of a precision switched capacitor (SC) oscillator. Features of this circuit include precision control over both frequency and amplitude, as well as means to ensure that oscillations start regardless of power-up sequence, reasonable offsets, etc. Many attributes of this oscillator are obtained by exploiting the unique properties o... View full abstract»

• ### A new integrable composite circuit with improved FET-like characteristics

Publication Year: 1985, Page(s):648 - 649
Cited by:  Papers (4)
| | PDF (330 KB)

A new composite circuit comprising five active devices (a JFET and four bipolar transistors) and three passive resistors is described and shown to exhibit FET-like characteristics with much improvement in thermal stability and transfer curve linearity over a wide range of input bipolar voltage. The input resistance of the proposed circuit is, however, equal to that of the FET with the additional a... View full abstract»

• ### A low-frequency CMOS triangle wave generator

Publication Year: 1985, Page(s):649 - 652
Cited by:  Papers (6)  |  Patents (4)
| | PDF (505 KB)

A monolithic variable frequency CMOS triangle wave generator is described along with experimental results. An external resistor connecting to the positive power supply tunes the frequency in the audio range of 30 to 2200 Hz. View full abstract»

• ### [Back inside cover - April 1985]

Publication Year: 1985, Page(s): b1
| PDF (150 KB)
• ### Charge-domain integrated circuits for signal processing

Publication Year: 1985, Page(s):562 - 570
Cited by:  Papers (8)  |  Patents (2)
| | PDF (1632 KB)

A new class of integrated circuits called charge-domain device has been developed for performing enhanced monolithic signal processing. All signal-processing operations are accomplished by splitting, routing and combining charge packets, thus overcoming many of the limitations of alternative devices such as charge-coupled device (CCD) split-electrode transversal filters and switched capacitor filt... View full abstract»

• ### Custom LSI/VLSI chip design productivity

Publication Year: 1985, Page(s):555 - 561
Cited by:  Papers (9)
| | PDF (1064 KB)

A description is given of an eight-parameter empirical model for determining design manpower for full custom digital LSI/VLSI (not standard cell or polycell). The model estimates design manpower from six generally available design characteristics. It fits the data from five different organizations with an average absolute error of 10%. Both merchant market suppliers an in-house captives are includ... View full abstract»

• ### Formal design procedures for pass transistor switching circuits

Publication Year: 1985, Page(s):531 - 536
Cited by:  Papers (69)  |  Patents (7)
| | PDF (1120 KB)

Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approa... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com