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Solid-State Circuits, IEEE Journal of

Issue 2 • Date April 1985

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Displaying Results 1 - 25 of 33
  • [Inside front cover - April 1985]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (April 1985)

    Page(s): 465 - 466
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    Freely Available from IEEE
  • Foreword (April 1985)

    Page(s): 467 - 468
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    Freely Available from IEEE
  • Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels

    Page(s): 469 - 480
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    A description is given of a novel CMOS gate array architecture for LSI/VLSI complexity. The new structure is based on the `gate isolation' technique for logic implementation, in addition to the programmability of the amount of routing channels. This concept uses double-level metal with the first contact level programmable for the circuit customization. The gate array has been designed in a 3-/spl mu/m Si-gate CMOS process. A maximum 2-input gate density of 290 gates/mm/SUP 2/ can be achieved. As a test vehicle for this novel gate array structure, a ninth-order LDI digital filter (4652 transistors) has been designed automatically with the aid of the gate array design system (GARDS) layout tool, on a 3/spl times/3 mm/SUP 2/ gate array size. In a first approach, the filter has been realized with the internal gate structure as used in classical gate arrays, and in a second approach the same filter has been laid out on 60% of the array size using the new concept. In this last version as much as 40% reduction of silicon area has been achieved. View full abstract»

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  • A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits

    Page(s): 481 - 488
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    Edge contact transistors are widely used in basic cells of gate-array circuits and custom designed circuits. The role of sheet and contact in affecting the performance of these transistors is investigated. A two-dimensional model has been developed to calculate the transistor's effective series resistance at various bias conditions. Very good correlation between the model and experiments has been obtained. It is found that different series resistances are observed in linear and saturation regions for edge contacts transistors in contrast to the conventional transistors. The results show that the effective series resistance of an edge contact transistor is nonuniform and is a complex function of the gate voltage, the drain voltage, and the linear or saturation bias conditions. View full abstract»

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  • An isolated vertical n-p-n transistor in an n-well CMOS process

    Page(s): 489 - 494
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    Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the MOS characteristics were unchanged. View full abstract»

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  • An integrated approach for hierarchical verification of VLSI mask artwork

    Page(s): 501 - 509
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    An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design methodology allows SLAVE to use the separate hierarchical representations in the logic, circuit, and layout models to completely verify the connectivity of the mask layout. SLAVE has been successfully adapted to both bipolar and CMOS technologies; it provides error detection down to specific signal nets and device nodes and is extremely fast. SLAVE typically runs under 70 min on a VAX 11/780 for a complex IC containing up to 50K discrete devices and is modeled using six levels of hierarchical nesting. View full abstract»

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  • The TimberWolf placement and routing package

    Page(s): 510 - 522
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    TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62% are possible. View full abstract»

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  • Analysis and design optimization of domino CMOS logic with application to standard cells

    Page(s): 523 - 530
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    The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implemented in both 5- and 3-/spl mu/m CMOS processes. View full abstract»

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  • A 16 bitx16 bit pipelined multiplier macrocell

    Page(s): 542 - 547
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    A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm. View full abstract»

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  • A methodology for the fast and testable implementation of state diagram specifications [logic design]

    Page(s): 548 - 554
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    A methodology is presented for the hierarchical structured design of state diagram specifications. It is based on a set of restrictions on the composition of the hierarchy that allows a design to be proven correct by construction. Furthermore, silicon primitives are introduced that permit a direct mapping of asynchronous and synchronous state diagrams. Special attention is paid to the use of scanpath testability enhancement. The design methodology and implementation technique combined facilitate a fast and area efficient integration of control structures. From the development of a DRAM controller IC, it is shown how layout design can be automated through several phases of standard cell design, permitting silicon compilation in the near future. View full abstract»

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  • An analog CMOS autopilot

    Page(s): 571 - 578
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    Results are presented of an analog LSI CMOS missile autopilot. The autopilot is a two-chip set which requires a total area of 210000 sq miles and consumes 700 mW of power. The set is fabricated in a double-poly p-well silicon-gate technology. The chips perform a wide array of analog functions, including precision filtering, full-wave demodulation, digital-to-analog conversion, limiting, pulsewidth modulation, and offset cancellation. A number of digital functions are also provided. The chip set was functionally correct on the first iteration after computer-aided verification. The output noise of the chip set is 6.5 mV, integrated over a bandwidth of 5-500 Hz. Results are presented over a temperature range of -55/spl deg/C to 125/spl deg/C. View full abstract»

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  • A custom data conversion subsystem for personal computers

    Page(s): 579 - 585
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    A `full custom' data conversion integrated circuit is described. it is used in a personal computer as an interface to the cassette recorder and the audio sound channel, and interfaces the joysticks to the computer. The chip contains a six-bit digital-to-analog converter (DAC), a three-channel multiplexer, a four-channel operational amplifier, and a comparator. The IC's unique features include the following: it uses a merged 96-collector p-n-p to produce the weighted current sources for the DAC; the bipolar op amp has a full rail-to-rail input capability; and the hysteresis in the comparator is accomplished using a cross-coupled current mirror technique. The chip operates with a single 5 V supply at 50 mW. View full abstract»

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  • A generalized layout rule generator

    Page(s): 589 - 591
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    As VLSI fabrication processes and systems become more complex, the number of layout rules required increases dramatically. A program is described that automatically creates and evaluates layout rules. The layout rules for a submicrometer CMOS process are generated and the variation of the density of a CMOS static RAM cell with process changes is illustrated. View full abstract»

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  • A 256K HCMOS ROM using a four-state cell approach

    Page(s): 598 - 602
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    A 256K HCMOS ROM design is discussed using a geometry-variable four-state cell for high packing density. Design, area, and process margin comparisons are made to other cell approaches. The architecture of the chip is shown and device performance is summarized. The 32K/spl times/8-bit ROM has typical access times of 200 ns with 11 mA of active current at 1000-ns cycle times and typical standby currents of 300 nA. Single-layer programming is performed with the poly layer, which is in the later stages of the process cycle than field-oxide or depletion implant programmed parts. The part is produced using an n-well HCMOS process with 2-/spl mu/m poly gate lengths. The part exhibits immunity from latchup without an epi substrate layer. This is primarily due to layout procedures to insure good substrate clamping and guardbanding. View full abstract»

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  • An EEPROM for microprocessors and custom logic

    Page(s): 603 - 608
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    An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/. View full abstract»

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  • A single-chip FM modem baseband CMOS LSI for land mobile telephone radio units

    Page(s): 617 - 622
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    A single-chip FM modulator/demodulator (modem) based LSI for the 800-MHz band land mobile radio unit has been developed. This LSI contains both digital and analog function blocks. The digital function block consists of high-speed digital PLL circuits such as a dual modulus prescaler, a programmable counter, and a phase frequency comparator for a 145 MHz direct FM modulator. The analog one consists of transmit and receive analog baseband circuits such as a voice limiter and various kinds of filters. In order to realize a high-speed and low power dissipation LSI, the pulse swallow method and switched capacitor technology have been used in the digital and analog circuits, respectively. The LSI chip is fabricated using a double polysilicon gate CMOS process with an effective channel length of 2 /spl mu/m. The chip size is 5.2 mm/spl times/5.8 mm. The circuit operates with a single voltage supply of 5 V. Typical power dissipation is 90 mW. View full abstract»

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  • An integrated six-path wave-SC filter

    Page(s): 632 - 640
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    Experimental results of a switched capacitor (SC) N-path filter integrated in a CMOS Si-gate technology are reported, with N=6. The circuit is based on the theory of wave-flow networks and uses only fully stray-eliminating (usually referred to as stray-insensitive) SC amplifier and integrator circuits. The two main drawbacks of N-path filters, i.e. unwanted mirror frequencies due to path mismatch and clock feedthrough located in the passbands, as solved by multiplexing large filter parts and by using a third-order high-pass reference filter, respectively. The integrated six-path filter features low power consumption due to the use of dynamic amplifiers. View full abstract»

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  • A switched capacitor oscillator with precision amplitude control and guaranteed start-up

    Page(s): 641 - 647
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    A description is given of the design and performance characteristics of a precision switched capacitor (SC) oscillator. Features of this circuit include precision control over both frequency and amplitude, as well as means to ensure that oscillations start regardless of power-up sequence, reasonable offsets, etc. Many attributes of this oscillator are obtained by exploiting the unique properties of switched capacitor circuits; the proposed circuit does not possess a direct active-RC counterpart. The authors include derivations of analytical expressions for output frequency, amplitude, and harmonic distortion. View full abstract»

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  • A new integrable composite circuit with improved FET-like characteristics

    Page(s): 648 - 649
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    A new composite circuit comprising five active devices (a JFET and four bipolar transistors) and three passive resistors is described and shown to exhibit FET-like characteristics with much improvement in thermal stability and transfer curve linearity over a wide range of input bipolar voltage. The input resistance of the proposed circuit is, however, equal to that of the FET with the additional advantage that it continues to be high even for positive input voltage. The proposed structure is fully compatible with silicon integrated circuit (IC) technology and may thus be commercially mass-produced as a three-terminal device with its terminals designated as gate, drain, and source. View full abstract»

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  • A low-frequency CMOS triangle wave generator

    Page(s): 649 - 652
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    A monolithic variable frequency CMOS triangle wave generator is described along with experimental results. An external resistor connecting to the positive power supply tunes the frequency in the audio range of 30 to 2200 Hz. View full abstract»

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  • [Back inside cover - April 1985]

    Page(s): b1
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    Freely Available from IEEE
  • Formal design procedures for pass transistor switching circuits

    Page(s): 531 - 536
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    Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared. View full abstract»

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  • Novel dynamic merged load technology

    Page(s): 537 - 541
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    Two new device concepts for dynamic ratioless inverter logic circuits are presented. Very high circuit density is achieved by replacing the traditional MOS dynamic load transistor with a novel load element which is merged with the switching transistor. Both device types can be implemented with a relatively standard double polysilicon CMOS process and are ideally suited for very low-power digital signal processors, serial memories and correlators, and digital image processors. View full abstract»

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  • Custom LSI/VLSI chip design productivity

    Page(s): 555 - 561
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    A description is given of an eight-parameter empirical model for determining design manpower for full custom digital LSI/VLSI (not standard cell or polycell). The model estimates design manpower from six generally available design characteristics. It fits the data from five different organizations with an average absolute error of 10%. Both merchant market suppliers an in-house captives are included in the sample. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan