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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1984

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Displaying Results 1 - 25 of 41
  • [Inside front cover - December 1984]

    Publication Year: 1984 , Page(s): f2
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    Freely Available from IEEE
  • 1984 Index IEEE Journal of Solid-State Circuits Vol. SC-19

    Publication Year: 1984 , Page(s): i1 - i15
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    Freely Available from IEEE
  • Table of contents (December 1984)

    Publication Year: 1984 , Page(s): 809 - 810
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    Freely Available from IEEE
  • Editor's Note (December 1984)

    Publication Year: 1984 , Page(s): 811
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    Freely Available from IEEE
  • Foreword (December 1984)

    Publication Year: 1984 , Page(s): 811 - 812
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    Freely Available from IEEE
  • A self-calibrating 15 bit CMOS A/D converter

    Publication Year: 1984 , Page(s): 813 - 819
    Cited by:  Papers (142)  |  Patents (36)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (885 KB)  

    A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate. View full abstract»

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  • A ratio-independent algorithmic analog-to-digital conversion technique

    Publication Year: 1984 , Page(s): 828 - 836
    Cited by:  Papers (152)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1061 KB)  

    An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-or... View full abstract»

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  • A monolithic 8-bit A/D converter with 120 MHz conversion rate

    Publication Year: 1984 , Page(s): 837 - 841
    Cited by:  Papers (15)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (745 KB)  

    A monolithic 8-bit flash A/D converter is described which digitizes a 40-MHz signal at a conversion rate of over 100 MHz. To obtain full resolution and high accuracy at ultrahigh speed operation, a three-stage comparator with small talk back and other new logic circuits were designed. The process used is a self-aligned bipolar technology. Signal-to-noise ratio of 45 dB was measured at the 30-MHz i... View full abstract»

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  • An 8 bit, 100 ms/s flash ADC

    Publication Year: 1984 , Page(s): 842 - 846
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (726 KB)  

    An 8-bit flash ADC capable of operation at a sampling rate higher than 100 MHz with only 1.2 W of power dissipation is described. This good performance is realized using: (1) a small transistor utilizing oxide isolation and a thick field oxide process with small parasitic capacitances; (2) an optimized design for speed, accuracy, and power; and (3) a simple comparator design with small component c... View full abstract»

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  • A single-chip 300 baud FSK modem

    Publication Year: 1984 , Page(s): 846 - 854
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (906 KB)  

    A 300-baud single-chip FSK modem implementing an RS-232 interface handshaking protocol is described. The device is a full duplex asynchronous modem that meets both Bell 103 and CCITT V.21 specifications. It incorporates the protocol required for automatic answer/originate, loss of carrier termination, and a 14-s abort timer. The device also implements analog and digital loopback capabilities for l... View full abstract»

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  • A single chip FSK modem

    Publication Year: 1984 , Page(s): 855 - 861
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (946 KB)  

    In the development of a fully LSI-designed single-chip 300-b/s asynchronous FSK modem, two `hard to beat' problems are: (1) to build both analog and digital circuits on-chip in-such a way that the modem performance is practically free from line noise and transmission distortion; and (2) to meet the requirement (CCITT V.21) of a +5 dBm level margin to discriminate carrier-on from carrier-off under ... View full abstract»

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  • A monolithic 1200 baud FSK CMOS modem

    Publication Year: 1984 , Page(s): 861 - 869
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1585 KB)  

    An integrated circuit that performs all the modulation, demodulation, filtering, and handshaking required to implement a modem that complies with the Bell 202 and CCITT V.23 standards is described. This double-poly CMOS device uses switched-capacitor techniques to operate at rate of up to 1200, 600, 150, 75, and 5 b/s. View full abstract»

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  • A single-chip frequency-shift keyed modem implemented using digital signal processing

    Publication Year: 1984 , Page(s): 869 - 877
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1240 KB)  

    A single-chip modem that uses digital signal processing (DSP) to perform the modem functions is described. The DSP modem is a complete single-chip modem which handles all of the popular international standards for frequency-shift keyed modems. These specifications include the Bell 103 and 202 specifications for North America, and the CCITT V.21 and V.23 specifications in Europe. The authors descri... View full abstract»

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  • A 1200 Bit/s QPSK full duplex modem

    Publication Year: 1984 , Page(s): 878 - 887
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1126 KB)  

    An NMOS integrated circuit is described that provides all the modulation, demodulation-filtering, and data-buffering functions for a 1200-b/s full-duplex voice-band modem. This modem is compatible with the Bell 212A modem, the Racal-Vadic 2400 modem, and the CCITT V.22 recommendation. All of the modems, options, and alternatives supported by these modems are also supported by the integrated circui... View full abstract»

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  • A z plane Lerner switched-capacitor filter

    Publication Year: 1984 , Page(s): 888 - 892
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (757 KB)  

    The design of a switched-capacitor filter that optimizes both amplitude and phase response simultaneously is described. Conceptually derived from a Lerner function, the filter architecture is efficient and simple. View full abstract»

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  • A programmable CMOS dual channel interface processor for telecommunications applications

    Publication Year: 1984 , Page(s): 892 - 899
    Cited by:  Papers (26)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1430 KB)  

    A CMOS analog VLSI chip for telecommunications applications has been designed in which many desirable line card features are programmable through a unique interface from the central switching office. The authors emphasize the circuit innovations of some key analog functions realized on the chip, specifically, the operational amplifier family, the precision bandgap reference circuit, and the line b... View full abstract»

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  • A single-chip high-voltage shallow-junction BORSHT-LSI

    Publication Year: 1984 , Page(s): 899 - 905
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1164 KB)  

    High-voltage and low-voltage BORSHT functions have been successfully incorporated into a single chip for the purpose of realizing a low-cost small-size subscriber-line interface circuit in a digital local switching system. The developed BORSHT-LSI is fabricated using a newly designed 350-V p-n-p-n device with shallow junctions 2 /spl mu/ in depth and a dielectrically isolated complementary bipolar... View full abstract»

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  • A CMOS line equalizer for a digital subscriber loop

    Publication Year: 1984 , Page(s): 906 - 912
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (897 KB)  

    An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer,... View full abstract»

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  • A CMOS narrow-band signaling filter with Q reduction

    Publication Year: 1984 , Page(s): 926 - 932
    Cited by:  Papers (1)  |  Patents (102)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (898 KB)  

    A circuit for extracting signaling information from its associated voice channel in frequency-division multiplexing has been integrated in metal gate CMOS technology. It uses a frequency translation technique that effectively enhances the Q of the filter to >100. It contains a programmable prefilter, a programmable modulator, and a highly selective bandpass filter. The frequency translation was... View full abstract»

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  • A linear NMOS depletion resistor and its application in an integrated amplifier

    Publication Year: 1984 , Page(s): 932 - 938
    Cited by:  Papers (20)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1033 KB)  

    A linear resistor has been realized by using NMOS depletion transistors operated in the triode region. While such a resistor is mainly intended for single-ended and first quadrant mode of conduction, where it achieves a nonlinearity of .03% full scale in the 0-10 V voltage range, it can also be used as a floating element and operated in the first as well as third quadrant mode of conduction (i.e. ... View full abstract»

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  • A monolithic 16-channels analog array normalizer

    Publication Year: 1984 , Page(s): 956 - 963
    Cited by:  Papers (30)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1483 KB)  

    A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages which are in the same ratios as the inputs with a peak amplitude controllable by the user. Response time is in the region of 1 /spl mu/s at full scale. The chip includes provisions for expansion to any number ... View full abstract»

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  • A single-chip 20-channel speech spectrum analyzer using a multiplexed switched-capacitor filter bank

    Publication Year: 1984 , Page(s): 964 - 970
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (960 KB)  

    A single-chip speech spectrum analyzer which contains a 20-channel filter bank, a 9-bit-resolution analog-to-digital converter, and a 396-bit buffer memory is described. Several efficient design techniques were used to realize the equivalent 308th-order transfer functions on a single chip monolithic MOS circuit. A new time-division-multiplexed switched-capacitor filter technique is introduced whic... View full abstract»

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  • A new Fahrenheit temperature sensor

    Publication Year: 1984 , Page(s): 971 - 977
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (736 KB)  

    A monolithic integrated circuit which provides an output voltage scaled proportionally to the Fahrenheit temperature without requiring the user to subtract a large constant offset is described. An advantage of this circuit is that the gain is inherently calibrated (e.g. to /spl plusmn/10.00 mV//spl deg/F) by simply trimming the offset error at room temperature. This behavior is shown to be a predi... View full abstract»

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  • A CMOS pulse density modulator for high-resolution A/D converters

    Publication Year: 1984 , Page(s): 995 - 996
    Cited by:  Papers (10)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (258 KB)  

    A high-performance pulse density modulator (PDM) has been fabricated using a 3.5-/spl mu/m CMOS silicon gate technology. The PDM comprises all the analog circuitry needed for an interpolative A/D converter. The PDM can be operated at sample rates of up to 12 MHz and offers a SNR of 80 dB over a baseband of 20 kHz, which corresponds to 13-bit equivalent A/D resolution. View full abstract»

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  • A CMOS low-distortion switched capacitor oscillator with instantaneous start-up

    Publication Year: 1984 , Page(s): 996 - 998
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (490 KB)  

    Experimental results on the oscillator indicate that good accuracy, low distortion, and instantaneous start-up are achieved. The sinusoidal oscillator has been fabricated in a 3-/spl mu/m CMOS double-poly process. The circuit is ideally suited for audio frequency applications such as DTMF tone generators and FSK modems. Further improvements in accuracy are expected if nonideal effects such as infi... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan