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IEEE Journal of Solid-State Circuits

Issue 2 • Date April 1984

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Displaying Results 1 - 25 of 25
  • [Inside front cover - April 1984]

    Publication Year: 1984, Page(s): f2
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  • Table of contents (April 1984)

    Publication Year: 1984, Page(s): 169
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  • Editorial: Our Hesitant Beginnings

    Publication Year: 1984, Page(s): 170
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  • The Origin of the Journal, the Council, and the Conference of Solid-State Circuits

    Publication Year: 1984, Page(s):171 - 173
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  • A four-state ROM using multilevel process technology

    Publication Year: 1984, Page(s):174 - 179
    Cited by:  Papers (15)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    A four-state ROM is described which reduces conventional two-state ROM matrix size by 50%. The four states are encoded in the matrix by varying device thresholds using multiple ion implants. This is called multilevel technology. The detection of matrix device type is determined by the length of time required for a linearly ramped word line to rise from 0 V to the point where the matrix device is t... View full abstract»

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  • A 40 ns 64 kbit junction-shorting PROM

    Publication Year: 1984, Page(s):187 - 194
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1422 KB)

    The memory is organized as 8192 words/spl times/8 bits. A memory cell consists of a programmable element composed of a p-n junction diode and a vertically connected p-n-p transistor. During programming, the programmable element is changed from the current-blocking state of a reverse diode to the current-conducting state of a shorted junction diode by using the diffused eutectic aluminum process (D... View full abstract»

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  • A novel clocking technique for VLSI circuit testability

    Publication Year: 1984, Page(s):207 - 212
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these r... View full abstract»

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  • An optically controllable negative resistance circuit constructed with optocouplers

    Publication Year: 1984, Page(s):223 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (773 KB)

    An optocoupler with a Darlington configuration at the output side can be used as a one port active device with a current-controlled negative resistance by simply connecting the input and output sides in cascade. The author proposes an optically controllable negative-resistance circuit constructed with optocouplers. The breakover voltage and the holding current of the negative-resistance characteri... View full abstract»

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  • A one-pin crystal oscillator for VLSI circuits

    Publication Year: 1984, Page(s):228 - 236
    Cited by:  Papers (19)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1463 KB)

    The oscillator features the same stability, reliability, and ease of use as the common Pierce oscillator; however, only one package pin and no external components other than the crystal need be dedicated to the oscillator. The design is quite general, and may be implemented in either NMOS or CMOS technologies, using only a moderate amount of silicon area. Design examples are given, and the fabrica... View full abstract»

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  • An extended Gummel-Poon model for an extreme range of temperature

    Publication Year: 1984, Page(s):251 - 253
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    An extended Gummel-Poon model qualified for extreme temperature requirements (-40/spl deg/C/spl les/T/spl les/150/spl deg/C) is presented. Comparing measurements and SPICE calculations of a bipolar transistor, the improvement of the modified model is demonstrated. The physical parameters determining the current gain characteristics are discussed. View full abstract»

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  • An up-transition edge-triggered single-shot pulse generator with Josephson devices

    Publication Year: 1984, Page(s):254 - 259
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (854 KB)

    The circuit is constructed with two cross-coupled DC flip-flops, resulting in a square-wave output signal without an external special clock signal. The circuit has been fabricated and its operating margin has been examined. An improved circuit for a wider operating margin is proposed and discussed. View full abstract»

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  • GaAs 1 kbit static RAM with self-aligned FET technology

    Publication Year: 1984, Page(s):260 - 262
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (569 KB)

    A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns addres... View full abstract»

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  • Dynamic logic CMOS circuits

    Publication Year: 1984, Page(s):263 - 266
    Cited by:  Papers (28)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (609 KB)

    A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design. View full abstract»

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  • An automatic error cancellation technique for higher accuracy A/D converters

    Publication Year: 1984, Page(s):266 - 268
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (427 KB)

    An automatic error cancellation technique for higher accuracy successive-approximation analog/digital (A/D) converters is described. The technique uses a binary-weighted capacitor array as its own reference, and no other special elements are required for capacitor mismatch compensation. Experimental results indicate that more than 14-bit A/D conversion can be performed on a conventional MOS IC chi... View full abstract»

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  • Correction to "Approximation of Wiring Delay in MOSFET LSI"

    Publication Year: 1984, Page(s): 271
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    First Page of the Article
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  • IEEE Solid-State Circuits Council Outstanding Development Award

    Publication Year: 1984, Page(s): 272
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  • [Back inside cover - April 1984]

    Publication Year: 1984, Page(s): b1
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  • Generation of high-frequency power oscillation by astable mode arcing with SCR switched inductor

    Publication Year: 1984, Page(s):269 - 271
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    High-frequency high-power oscillation can be generated by a two-terminal and feedback oscillator. In the former, the negative resistance portion is separated from the frequency determining part so these can use a solid-state negative resistance switching device. However, the power output capability is limited in single-stage operation. Using an inductor-switched SCR device, an arc can be establish... View full abstract»

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  • STL versus ISL: an experimental comparison

    Publication Year: 1984, Page(s):195 - 206
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1688 KB)

    Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-μm and 2-μm oxide isolated processes and characterized over the military temperature range (-55 to +125°C ambient). The temperature coefficient of the average propagation delay (t˜/SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficie... View full abstract»

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  • Prediction of error probabilities for integrated digital synchronizers

    Publication Year: 1984, Page(s):236 - 244
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1680 KB)

    Synchronization errors occur when asynchronous digital signals are received by clocked digital systems. Digital synchronizers are designed to minimize the probability of such errors. Empirical determination of error probabilities, as used in the past, is not a viable method for large-scale integrated circuit because it is cumbersome, interferes with the circuit performance, and does not account fo... View full abstract»

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  • Delay time and signal propagation in large-scale integrated circuits

    Publication Year: 1984, Page(s):262 - 263
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Delay time and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry-independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0.01 ps. At the opposite extreme, values appropriate to convention... View full abstract»

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  • Monolithic array of optoelectronic broad-band switches

    Publication Year: 1984, Page(s):219 - 223
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    The response of monolithic arrays of GaAs photoconductors to optical intensity modulation signals and their feasibility of operating as crosspoint arrays in integrated broadband switch matrices are investigated. It is found that individual photoconductors can switch signals at frequencies of up to 1.3 GHz with isolation better than 70 dB and switching time less than 10 ns. In a 2×2 monolithi... View full abstract»

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  • Modeling of backgating effects on GaAs digital integrated circuits

    Publication Year: 1984, Page(s):245 - 250
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    The characteristics of GaAs MESFETs are analyzed and modeled, and the results are used to simulate the performance of GaAs digital integrated circuits in the presence of backgating. The degradation of the output current of a MESFET in a circuit is theoretically calculated by treating the channel-substrate interface as a p-n junction, with the junction bias being linearly proportional to the voltag... View full abstract»

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  • Functional testing of EPROMs

    Publication Year: 1984, Page(s):212 - 218
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB)

    The aim of this paper is to develop a testing scheme for EPROM memories. The starting point is the assumed general model of EPROM memory logic structure. For this model, an adequate fault model is developed. The class of faults taken into consideration includes faults in input-output buffers, faults in address decoding circuitry, and faults in memory cell arrays. The proposed testing scheme makes ... View full abstract»

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  • Novel circuits for high speed ROMs

    Publication Year: 1984, Page(s):180 - 186
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    Novel approaches in circuit design, such as overlap timing without precharge, complementary ROM cells with two access lines, and overall chain-delay optimization, greatly increase the operational speed of ROMs. The innovative circuits fabricated with an advanced CMOS/SOS process resulted in an experimental 18-kbit (2K×9) look-up ROM performing a cycle time of 4 ns, a silicon area of 7.2 kmil... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan