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IEEE Journal of Solid-State Circuits

Issue 1 • Date Feb. 1984

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Displaying Results 1 - 25 of 36
  • [Inside front cover - February 1984]

    Publication Year: 1984, Page(s): f2
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  • Table of contents (February 1984)

    Publication Year: 1984, Page(s):1 - 2
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  • Foreword (February 1984)

    Publication Year: 1984, Page(s):3 - 4
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  • A subnanosecond 2000 gate array with ECL 100K compatibility

    Publication Year: 1984, Page(s):5 - 9
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (898 KB)

    Describes a subnanosecond-gate array with 2000 gates fabricated by an advanced bipolar process. A 700-ps delay time was achieved for a basic ECL gate under a general usage condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, with power dissipation of 1.9 mW/gate. A 450-MHz typical toggle frequency has been obtained by using a series-gated flip-flop. Utilizing an integrated computer-aided des... View full abstract»

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  • A gallium arsenide SDFL gate array with on-chip RAM

    Publication Year: 1984, Page(s):10 - 22
    Cited by:  Papers (6)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2316 KB)

    Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with... View full abstract»

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  • Automated gate array scaling

    Publication Year: 1984, Page(s):23 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (473 KB)

    A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated. View full abstract»

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  • A mixed EFL/I/sup 2/L digital telecommunication integrated circuit

    Publication Year: 1984, Page(s):26 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (979 KB)

    A bipolar integrated circuit has been designed as part of a VLSI upgrade of an existing digital switching circuit. The chip exploits the OXIL (oxide isolated) process which makes it possible to use both high-gain `up' and `down' devices, for I/SUP 2/L (integrated injection logic) and EFL (emitter function logic) respectively. This allowed the circuit designers to tailor power consumption, circuit ... View full abstract»

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  • A three-dimensional CMOS design methodology

    Publication Year: 1984, Page(s):37 - 39
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB)

    A technology-updatable design methodology for three-dimensional CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: (1) technology level, (2) mask level, (3) transistor level, and (4) logic level. A novel transistor-level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of des... View full abstract»

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  • A novel wide dynamic range silicon photodetector and linear imaging array

    Publication Year: 1984, Page(s):41 - 48
    Cited by:  Papers (38)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1129 KB)

    A silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed. This photodetector, which can be integrated on the same chip with MOSFET circuits or CCDs, provides an analog voltage signal over a wide dynamic range. Photodetector and arrays showed, in the visible spectrum an incoming radiation-detection light-intensity dynamic range of greater than 10/SUP 7/. In addition, ... View full abstract»

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  • A CCD color signal separation IC for single-chip color imagers

    Publication Year: 1984, Page(s):49 - 54
    Cited by:  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1173 KB)

    A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a color filter array utilizing Bayer geo... View full abstract»

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  • Analog CMOS Building Blocks for Custom and Semicustom Applications

    Publication Year: 1984, Page(s):55 - 61
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1149 KB)

    Standard analog building blocks developed for use in custom and semicustom LSI and VLSI designs are described. The analog blocks are built using a digital CMOS process modified to include high-value resistors and voltage independent capacitors. Designs for operational amplifiers, programmable voltage sources, comparators, band gap voltage references, unit resistors, capacitors, and n-p-n devices a... View full abstract»

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  • An NMOS buffer amplifier

    Publication Year: 1984, Page(s):69 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A wideband buffer amplifier, suitable for amplifying fast pulses originating from a high-impedance capacitive source (photodiode, transducer, biological probe, etc.) has been designed and fabricated using 3-5/spl mu/m NMOS technology. The circuit exhibits wide bandwidth (4.6 MHz) and fast rise time (100 ns) even for large capacitances (~10 pF) at its input and output terminals. A wide range of inp... View full abstract»

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  • A new method for detecting electromigration failure in VLSI metallization

    Publication Year: 1984, Page(s):98 - 99
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (275 KB)

    A method has been developed for metallization predictions using a continuous resistance-monitoring technique. A useful lifetime criterion, based on measured resistance changes has been determined that is more sensitive and consequently more accurate than present catastrophic failure techniques. View full abstract»

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  • A parametric short-channel MOS transistor model for subthreshold and strong inversion current

    Publication Year: 1984, Page(s):100 - 112
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1895 KB)

    The authors present a parametric model which covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel-length modulation. The model simulates accurately the current characteristics as ... View full abstract»

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  • An experimental method for the determination of the saturation point of a MOSFET

    Publication Year: 1984, Page(s):113 - 117
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (741 KB)

    This paper presents an extraction technique which determines the drain voltages and currents at saturation directly from experimental data. The technique makes use of both drain current and conductance data. In addition to V/SUB DSS/ and I/SUB DSS/, parameters for the characterization of the saturation region may be extracted via this technique. View full abstract»

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  • Minimum test chip sample size selection for characterizing process parameters

    Publication Year: 1984, Page(s):123 - 130
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1410 KB)

    A method for determining a test-chip sample size to estimate effectively the electrical parameter distributions on an integrated circuit wafer is presented. This method gives relations among sample size and the figure of merit for four statistical techniques (trimmed mean, biweighted mean, median, and arithmetic mean) by which estimates are calculated. To demonstrate its use, the method has been a... View full abstract»

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  • A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

    Publication Year: 1984, Page(s):130 - 135
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1113 KB)

    SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process, but process-induced variations in these parameters occur within a chip or from chip to chip. Values for the model parameters used in simulators are usually obtained from measurements on test structures along the per... View full abstract»

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  • Low-noise high-speed optical receiver for fiber optic systems

    Publication Year: 1984, Page(s):155 - 157
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    A low-noise preamplifier for fiber-optic systems which uses a GaAs FET as input stage is described. It exhibits high input impedance which is shown to yield a low-noise performance insensitive to 1/f noise, an otherwise dominant component with a GaAs FET input stage. A modified version serves as a broadband general-purpose amplifier terminated at the input and output by 50 /spl Omega/. A novel gai... View full abstract»

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  • Correction to "Minimum Propagation Delays in VLSI"

    Publication Year: 1984, Page(s): 162
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    First Page of the Article
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  • IEEE copyright form

    Publication Year: 1984, Page(s):163 - 164
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  • Solid-State Circuits Council Fellowship (February 1984)

    Publication Year: 1984, Page(s): 165
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  • IEEE Solid-State Circuits Council Fellow Evaluations

    Publication Year: 1984, Page(s): 167
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  • IEEE Fellow Nomination Guidelines

    Publication Year: 1984, Page(s): 168
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  • [Back inside cover - February 1984]

    Publication Year: 1984, Page(s): b1
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  • Design methodology of a 1.2-μm double-level-metal CMOS technology

    Publication Year: 1984, Page(s):81 - 91
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2192 KB)

    An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-μm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded d... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com