By Topic

Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1978

Filter Results

Displaying Results 1 - 25 of 33
  • [Inside front cover - December 1978]

    Publication Year: 1978 , Page(s): f2
    Save to Project icon | Request Permissions | PDF file iconPDF (156 KB)  
    Freely Available from IEEE
  • 1978 Index IEEE Journal of Solid-State Circuits Vol. SC-13

    Publication Year: 1978 , Page(s): i1 - i11
    Save to Project icon | Request Permissions | PDF file iconPDF (2469 KB)  
    Freely Available from IEEE
  • Table of contents (December 1978)

    Publication Year: 1978 , Page(s): 733 - 936
    Save to Project icon | Request Permissions | PDF file iconPDF (126 KB)  
    Freely Available from IEEE
  • Foreword - Special Issue on Analog Circuits

    Publication Year: 1978 , Page(s): 734 - 735
    Save to Project icon | Request Permissions | PDF file iconPDF (330 KB)  
    Freely Available from IEEE
  • A monolithic 10-bit A/D using I/sup 2/L and LWT thin-film resistors

    Publication Year: 1978 , Page(s): 736 - 745
    Cited by:  Papers (9)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1594 KB)  

    Describes the function, circuit details, and performance of a monolithic 10-bit A/D converter. The converter is a successive approximation type using linear compatible I/SUP 2/L for the SAR. The converter is completely self-contained, including both clock and voltage reference. Biasing is arranged to take advantage of naturally occurring interfaces in the circuitry, simplifying the overall circuit in comparison to discrete or hybrid approaches. The processing also includes on-chip thin-film resistors which are laser-wafer-trimmed (LWR) for overall accuracy and temperature stability. The finished circuits operate with no missing codes over the -55/spl deg/ to +125/spl deg/C temperature range. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A microprocessor-compatible high-speed 8-bit DAC

    Publication Year: 1978 , Page(s): 746 - 753
    Cited by:  Papers (1)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the converter appears as a memory location to the microprocessor. It can be programmed to operate in a wide variety of modes and can interface with the fastest MOS and TTL microprocessors. The converter offers high-speed multiplying operation and an output current mode multiplexer. Status latches are provided to store multiplexer and code select commands. Nonsaturating multilevel logic operating nearly in the linear region provides gate delays of less than 5 ns when fabricated on the same chip with precision linear functions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance NMOS operational amplifier

    Publication Year: 1978 , Page(s): 760 - 766
    Cited by:  Papers (59)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1003 KB)  

    A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 /spl mu/V; C-message weighted noise -5 dBrnC; and 0.1-percent settling time, 2.5 /spl mu/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new NMOS temperature-stable voltage reference

    Publication Year: 1978 , Page(s): 767 - 774
    Cited by:  Papers (49)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1269 KB)  

    An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS voltage reference

    Publication Year: 1978 , Page(s): 774 - 778
    Cited by:  Papers (49)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    A method for developing a reference voltage in CMOS integrated circuits is described. The circuit uses MOS devices operating in the weak inversion region, as well as a bipolar device formed without process modifications. A brief description of this region of operation is given. Then, the principle of the suggested voltage reference is explained and the final implementation is presented. Higher order effects are discussed, and results from an integrated prototype given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new single-chip C/sup 2/MOS A/D converter for microprocessor systems-Penta-Phase Integrating C/sup 2/MOS A/D converter

    Publication Year: 1978 , Page(s): 779 - 785
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1204 KB)  

    A new unique conversion technique named the `Penta-Phase Integration' method, applied to a single-chip C/SUP 2/MOS 12-bit analog-to-digital converter designed for microprocessor system, is introduced and described. The newly developed device, fabricated with a standard metal gate CMOS process including an 8-channel multiplexer and TTL compatibility, has several features: unipolar- and ratiometric-conversion can be performed; conversion accuracy within /spl plusmn/0.05 percent of full scale over the -35/spl deg/C-+85/spl deg/C temperature range can be obtained; conversion time is 1.1 ms at a 20 MHz clock frequency, and the device can be operated with a single 5 V power supply and 6 mW power consumption at a 4 MHz clock frequency. The new technique essentially incorporated several methods which divide one conversion cycle into five-phases, accomplish minimization of the error caused by comparator response delay, provide several narrow flat phases to eliminate switching errors due to parasitic capacitance, and enable high clock frequency operation in digital circuits by utilizing C/SUP 2/MOS circuit technology and a synchronized configuration for counters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A single chip all-MOS 8-bit A/D converter

    Publication Year: 1978 , Page(s): 785 - 791
    Cited by:  Papers (30)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1274 KB)  

    A new analog-to-digital (A/D) conversion technique compatible with standard single channel MOS technology is described. This technique uses a string of equal value diffused resistors and a matrix of analog switches to perform high-speed successive approximation conversion. The comparator function is realized by a chopper-type amplifier to reduce the inherently high input offset voltages of MOS differential stages. Typical performance characteristics taken from a large sample of ICs are presented; a resolution of 8 bits has been achieved with a conversion time of 20 /spl mu/s. The complete system is fabricated on a 14000 mil/SUP 2/ die. Due to its small relative size, this A/D technique has been incorporated as part of a larger CODEC system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • MOS switched capacitor ladder filters

    Publication Year: 1978 , Page(s): 806 - 814
    Cited by:  Papers (56)  |  Patents (109)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1472 KB)  

    A new technique for designing precision, fully integrated, high-order filters using standard MOS technology is described. Switched capacitor integrators have been used to realize long time constants in small areas, and by interconnecting these integrators in a `leapfrog' configuration, monolithic high-order filters have been implemented with transfer functions that are very insensitive to component variations. Experimental results are presented for an NMOS fifth-order Chebyshev low-pass ladder filter with 0.1-dB passband ripple, a cutoff frequency of 3.4 kHz when clocked at 128 kHz, and a dynamic range of 83 dB. An efficient method for implementing transmission zeros is also presented, along with a complete design example, and additional experimental results for a third-order elliptic low-pass ladder filter which achieved 90-dB dynamic range, with a total power dissipation of 18 mW in a die area of 4400 mil/SUP 2/. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A completely integrated thirty-two-point chirp Z transform [CCD IC realisation]

    Publication Year: 1978 , Page(s): 822 - 831
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1550 KB)  

    A monolithic 32-point DFT using the chirp Z transform (CZT) algorithm has been designed and fabricated using an n-channel two-level polysilicon coplanar electrode process. The detailed design and operation of this first fully integrated CCD chirp Z transform are discussed, and some spectral analysis applications for a CCD CZT are described. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A MOS cursive-character generator [for deflection system of CRT graphic display]

    Publication Year: 1978 , Page(s): 832 - 837
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1077 KB)  

    Cursive characters can be made to be more readable, more attractive, and better suited to the operation of graphic CRT terminals than the usual dot-matrix type; a system using cursive-type characters achieves much higher writing rate while requiring much less bandwidth than that using dot-matrix-type characters. An economical method of generating the x, y, and z analog signals for forming cursive characters with the deflection system of a CRT is presented. A circuit design embodying a complete 48-stroke character generator on a single MOS integrated circuit is described. The IC accepts 7-bit ASCII code and outputs x, y, and z analog signals to generate any one of 32 standard ASCII characters in 5 /spl mu/s. Additional groups of 32 characters can be added by merely paralleling additional chips. The entire 32 character digital and analog function has been implemented on a single self-contained 16-pin silicon-gate MOS chip 125/spl times/165 mil in size. Character encoding on the chip is accomplished in one mask at the diffusion step, and a straightforward mask-generation procedure has been developed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-voltage IC timer

    Publication Year: 1978 , Page(s): 847 - 852
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB)  

    The design of a low-voltage micropower timer is described. It is well known that if standard analog integrated n-p-n transistors are connected in a simple diode-biased current sink arrangement, the saturation of one of the transistors in the string drastically reduces the collector currents in the other transistors. By using this effect to indicate the onset of saturation, the timing capacitor's end-of-discharge voltage is sensed at one V/SUB cc(sat)/ above ground. When used as a low-duty cycle timer, or as a monostable, the circuit can achieve accuracies comparable to that of the industry standard 555 timer and can operate at supply voltages as low as 1 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A precision FET-less sample-and-hold with high charge-to-droop current ratio

    Publication Year: 1978 , Page(s): 864 - 873
    Cited by:  Papers (3)  |  Patents (108)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1370 KB)  

    A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions are changed under logic control; it functions as a fast follower in the sample mode, and as a low input current amplifier in the hold mode. Performance characteristics include: 3.5-/spl mu/s acquisition time to 0.1 percent with a 5000-pF hold capacitor, 50 pA of droop current from 0 to 70/spl deg/C, 10/SUP 9/ charge-to-droop current ratio, and 0.3 mV of zero-scale error. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A versatile monolithic IC building-block for light-sensing applications

    Publication Year: 1978 , Page(s): 873 - 881
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1409 KB)  

    An all-bipolar building-block consisting of a linear light-to-current converter, a voltage comparator, and a voltage reference has been developed. This new general purpose IC combines the advantages of silicon photodiode light sensors with the linear signal processing capability of bipolar integrated transistors. In achieving this marriage, new circuit techniques were developed in order to operate at the very low current levels (<1 nA) and over the wide dynamic range of the light input. Besides their normal sensory function, photodiodes were made to serve as active elements in the circuit, taking part in biasing and acting as active loads in circuits that operate entirely on photocurrents. Use of these techniques boosted overall performance and eliminated the need for a light shield over the active-device portion of the die. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simple model for the determination of I/sup 2/L base current components

    Publication Year: 1978 , Page(s): 899 - 905
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1035 KB)  

    Assuming uniform impurity and mobility profiles and a trapezoidal minority carrier distribution a simple structure-oriented model for an upward-operated I/SUP 2/L n-p-n transistor has been derived which accurately describes its DC properties. Its validity is demonstrated with reference to some examples. With the aid of this model it is now possible to determine the various base current components by measuring the collector current I/SUB c/ (V/SUB be/), the base current I/SUB b/(V/SUB be/), and the recollection current I/SUB rec/(V/SUB be/) directly at the I/SUP 2/L gate without the need of special test structures. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A functional MOS circuit for achieving the bilinear transformation in switched capacitor filters

    Publication Year: 1978 , Page(s): 906 - 909
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (523 KB)  

    Recently, a new technique for filtering in MOS LSI using switched capacitors has been demonstrated (see ibid., vol.SC-12, p.592, 1977). Basically, the technique involves the replacement of resistors, in continuous active RC filter designs, with an analogous circuit using switches and capacitors in a sampled-analog equivalent. The approach creates a problem, however, in that the switched capacitor structures do not directly simulate the equivalent resistors over the useful frequency range. This leads to the necessity for Z-transform analysis, and causes the sampled analog circuit behavior to degrade from the simplicity of the continuous active equivalent. A solution to the problem of realising the bilinear transformation in a switched capacitor network with experimental verification is given. The solution is presented in the context of an active integrator, but is quite general. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A comparison of high-speed I/sup 2/L structures

    Publication Year: 1978 , Page(s): 909 - 911
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB)  

    A comparison is made between the Schottky coupled I/SUP 2/L structure, low downward beta I/SUP 2/L, and conventional double base fully implanted I/SUP 2/L. All of these were fabricated together on a single chip so that a direct comparison could be made. The results of both measured and predicted ring oscillators are presented. Finally, the results of a D-type flip flop connected as a divide-by-two show that the SCTL gate is superior. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • I/sup 2/L design in standard bipolar process

    Publication Year: 1978 , Page(s): 914 - 917
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB)  

    A calculation method for I/SUP 2/L gain parameters as a function of the design is presented. The small current gain of I/SUP 2/L inverters in a standard bipolar process is improved by inserting the shallow n/SUP +/-diffusion into the p-n-p base, thus providing for correct operation of four-collector devices. DC and AC characteristics are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interdigitated I/sup 2/L structures

    Publication Year: 1978 , Page(s): 917 - 921
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (617 KB)  

    The isolation of I/SUP 2/L structures in a conventional bipolar LSI technology is provided by a shallow or a deep n/SUP +/ collar. If part of this collar is replaced with an injector, an interdigitated I/SUP 2/L structure results. The structure has less delay at intermediate current levels compared to the conventional I/SUP 2/L layout. The reduction in delay is significant if the replaced collar is a shallow n/SUP +/. This improved performance is obtained at the expense of packing density. This correspondence presents the structure and analyzes its performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back inside cover - December 1978]

    Publication Year: 1978 , Page(s): b1
    Save to Project icon | Request Permissions | PDF file iconPDF (144 KB)  
    Freely Available from IEEE
  • On-chip power supply for 110 V line input

    Publication Year: 1978 , Page(s): 882 - 886
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A simple integrated power supply circuit in ESFI-SOS technology with only one external capacitor is presented. The circuit, which can directly be applied to 110 V AC line voltages, comprises a bridge rectifier, a `lambda'-type current switch, and a series regulator with overload protection. Because of the relatively small area consumption (6 mm/SUP 2/) the circuit to be supplied can easily be integrated on the same chip. Experimental results show a DC output power of about 100 mW (10 V/10 mA). Due to the lambda-type current switching high efficiencies of more than 30 percent are achieved. With some additional device modifications to increase breakdown voltage it should be possible to operate such circuits also with 220 V AC line voltages. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of integrated analog CMOS circuits-a multichannel telemetry transmitter [single-stage differential amplifier]

    Publication Year: 1978 , Page(s): 799 - 805
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    A single-stage differential amplifier, implemented in a standard metal-gate process, serves as a basis for consideration of specific characteristics of analog CMOS circuits. The dependence of important circuit parameters like open-loop gain and gain-bandwidth product on transistor geometries, and biasing current are derived. Furthermore, it is shown how to improve the amplifier characteristics by optimizing the layout. The differential amplifier stage is compared with an equivalent one based on a standard bipolar process. This comparison shows that the CMOS stage exceeds in the low-current region (nanoamperes) not only the possible voltage gain but also the gain-bandwidth product of a bipolar stage. The results are applied to the design of a multichannel telemetry transmitter for patient monitoring. The transmitter chip incorporates a digital part for the multiplex control and a precise analog part for the modulation unit. The modulator is a voltage controlled oscillator and consists of two parts: a voltage-to-current converter and a current controlled oscillator. The linear range of the voltage-to-current converter is limited to at most three decades due to the offset of MOS transistors. The current controlled oscillator, however, has a linear range of more than seven decades. This was made possible by applying a new design principle, which is specific for CMOS technology. Besides the large linear range the multivibrator has excellent temperature stability. The chip area is 4 mm/SUP 2/. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan