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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1978

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Displaying Results 1 - 25 of 33
  • [Inside front cover - December 1978]

    Publication Year: 1978 , Page(s): f2
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    Freely Available from IEEE
  • 1978 Index IEEE Journal of Solid-State Circuits Vol. SC-13

    Publication Year: 1978 , Page(s): i1 - i11
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    Freely Available from IEEE
  • Table of contents (December 1978)

    Publication Year: 1978 , Page(s): 733 - 936
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    Freely Available from IEEE
  • Foreword - Special Issue on Analog Circuits

    Publication Year: 1978 , Page(s): 734 - 735
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    Freely Available from IEEE
  • A monolithic 10-bit A/D using I/sup 2/L and LWT thin-film resistors

    Publication Year: 1978 , Page(s): 736 - 745
    Cited by:  Papers (9)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1594 KB)  

    Describes the function, circuit details, and performance of a monolithic 10-bit A/D converter. The converter is a successive approximation type using linear compatible I/SUP 2/L for the SAR. The converter is completely self-contained, including both clock and voltage reference. Biasing is arranged to take advantage of naturally occurring interfaces in the circuitry, simplifying the overall circuit... View full abstract»

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  • A microprocessor-compatible high-speed 8-bit DAC

    Publication Year: 1978 , Page(s): 746 - 753
    Cited by:  Papers (1)  |  Patents (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1084 KB)  

    The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the conv... View full abstract»

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  • High-performance NMOS operational amplifier

    Publication Year: 1978 , Page(s): 760 - 766
    Cited by:  Papers (59)  |  Patents (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1003 KB)  

    A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 ... View full abstract»

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  • A new NMOS temperature-stable voltage reference

    Publication Year: 1978 , Page(s): 767 - 774
    Cited by:  Papers (52)  |  Patents (20)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1269 KB)  

    An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS tran... View full abstract»

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  • A CMOS voltage reference

    Publication Year: 1978 , Page(s): 774 - 778
    Cited by:  Papers (50)  |  Patents (11)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (748 KB)  

    A method for developing a reference voltage in CMOS integrated circuits is described. The circuit uses MOS devices operating in the weak inversion region, as well as a bipolar device formed without process modifications. A brief description of this region of operation is given. Then, the principle of the suggested voltage reference is explained and the final implementation is presented. Higher ord... View full abstract»

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  • A new single-chip C/sup 2/MOS A/D converter for microprocessor systems-Penta-Phase Integrating C/sup 2/MOS A/D converter

    Publication Year: 1978 , Page(s): 779 - 785
    Cited by:  Papers (1)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1204 KB)  

    A new unique conversion technique named the `Penta-Phase Integration' method, applied to a single-chip C/SUP 2/MOS 12-bit analog-to-digital converter designed for microprocessor system, is introduced and described. The newly developed device, fabricated with a standard metal gate CMOS process including an 8-channel multiplexer and TTL compatibility, has several features: unipolar- and ratiometric-... View full abstract»

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  • A single chip all-MOS 8-bit A/D converter

    Publication Year: 1978 , Page(s): 785 - 791
    Cited by:  Papers (31)  |  Patents (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1274 KB)  

    A new analog-to-digital (A/D) conversion technique compatible with standard single channel MOS technology is described. This technique uses a string of equal value diffused resistors and a matrix of analog switches to perform high-speed successive approximation conversion. The comparator function is realized by a chopper-type amplifier to reduce the inherently high input offset voltages of MOS dif... View full abstract»

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  • MOS switched capacitor ladder filters

    Publication Year: 1978 , Page(s): 806 - 814
    Cited by:  Papers (59)  |  Patents (109)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1472 KB)  

    A new technique for designing precision, fully integrated, high-order filters using standard MOS technology is described. Switched capacitor integrators have been used to realize long time constants in small areas, and by interconnecting these integrators in a `leapfrog' configuration, monolithic high-order filters have been implemented with transfer functions that are very insensitive to componen... View full abstract»

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  • A completely integrated thirty-two-point chirp Z transform [CCD IC realisation]

    Publication Year: 1978 , Page(s): 822 - 831
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1550 KB)  

    A monolithic 32-point DFT using the chirp Z transform (CZT) algorithm has been designed and fabricated using an n-channel two-level polysilicon coplanar electrode process. The detailed design and operation of this first fully integrated CCD chirp Z transform are discussed, and some spectral analysis applications for a CCD CZT are described. View full abstract»

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  • A MOS cursive-character generator [for deflection system of CRT graphic display]

    Publication Year: 1978 , Page(s): 832 - 837
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1077 KB)  

    Cursive characters can be made to be more readable, more attractive, and better suited to the operation of graphic CRT terminals than the usual dot-matrix type; a system using cursive-type characters achieves much higher writing rate while requiring much less bandwidth than that using dot-matrix-type characters. An economical method of generating the x, y, and z analog signals for forming cursive ... View full abstract»

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  • A low-voltage IC timer

    Publication Year: 1978 , Page(s): 847 - 852
    Cited by:  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (794 KB)  

    The design of a low-voltage micropower timer is described. It is well known that if standard analog integrated n-p-n transistors are connected in a simple diode-biased current sink arrangement, the saturation of one of the transistors in the string drastically reduces the collector currents in the other transistors. By using this effect to indicate the onset of saturation, the timing capacitor's e... View full abstract»

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  • A precision FET-less sample-and-hold with high charge-to-droop current ratio

    Publication Year: 1978 , Page(s): 864 - 873
    Cited by:  Papers (3)  |  Patents (108)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1370 KB)  

    A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions ar... View full abstract»

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  • A versatile monolithic IC building-block for light-sensing applications

    Publication Year: 1978 , Page(s): 873 - 881
    Cited by:  Papers (1)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1409 KB)  

    An all-bipolar building-block consisting of a linear light-to-current converter, a voltage comparator, and a voltage reference has been developed. This new general purpose IC combines the advantages of silicon photodiode light sensors with the linear signal processing capability of bipolar integrated transistors. In achieving this marriage, new circuit techniques were developed in order to operate... View full abstract»

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  • A simple model for the determination of I/sup 2/L base current components

    Publication Year: 1978 , Page(s): 899 - 905
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1035 KB)  

    Assuming uniform impurity and mobility profiles and a trapezoidal minority carrier distribution a simple structure-oriented model for an upward-operated I/SUP 2/L n-p-n transistor has been derived which accurately describes its DC properties. Its validity is demonstrated with reference to some examples. With the aid of this model it is now possible to determine the various base current components ... View full abstract»

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  • A functional MOS circuit for achieving the bilinear transformation in switched capacitor filters

    Publication Year: 1978 , Page(s): 906 - 909
    Cited by:  Papers (7)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (523 KB)  

    Recently, a new technique for filtering in MOS LSI using switched capacitors has been demonstrated (see ibid., vol.SC-12, p.592, 1977). Basically, the technique involves the replacement of resistors, in continuous active RC filter designs, with an analogous circuit using switches and capacitors in a sampled-analog equivalent. The approach creates a problem, however, in that the switched capacitor ... View full abstract»

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  • A comparison of high-speed I/sup 2/L structures

    Publication Year: 1978 , Page(s): 909 - 911
    Request Permissions | Click to expandAbstract | PDF file iconPDF (589 KB)  

    A comparison is made between the Schottky coupled I/SUP 2/L structure, low downward beta I/SUP 2/L, and conventional double base fully implanted I/SUP 2/L. All of these were fabricated together on a single chip so that a direct comparison could be made. The results of both measured and predicted ring oscillators are presented. Finally, the results of a D-type flip flop connected as a divide-by-two... View full abstract»

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  • I/sup 2/L design in standard bipolar process

    Publication Year: 1978 , Page(s): 914 - 917
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (751 KB)  

    A calculation method for I/SUP 2/L gain parameters as a function of the design is presented. The small current gain of I/SUP 2/L inverters in a standard bipolar process is improved by inserting the shallow n/SUP +/-diffusion into the p-n-p base, thus providing for correct operation of four-collector devices. DC and AC characteristics are discussed. View full abstract»

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  • Interdigitated I/sup 2/L structures

    Publication Year: 1978 , Page(s): 917 - 921
    Request Permissions | Click to expandAbstract | PDF file iconPDF (617 KB)  

    The isolation of I/SUP 2/L structures in a conventional bipolar LSI technology is provided by a shallow or a deep n/SUP +/ collar. If part of this collar is replaced with an injector, an interdigitated I/SUP 2/L structure results. The structure has less delay at intermediate current levels compared to the conventional I/SUP 2/L layout. The reduction in delay is significant if the replaced collar i... View full abstract»

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  • [Back inside cover - December 1978]

    Publication Year: 1978 , Page(s): b1
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    Freely Available from IEEE
  • Modeling of Schottky coupled transistor logic

    Publication Year: 1978 , Page(s): 893 - 898
    Request Permissions | Click to expandAbstract | PDF file iconPDF (896 KB)  

    The SCTL gate which promises increased speed and reduced power is discussed. It involves the use of a single lowly doped collector incorporating Schottky diodes to decode the output. A complete electrical model is formulated and compared with experimental results. The model is then used to optimize this structure with respect to extrinsic and intrinsic base doping and collector doping, and it resu... View full abstract»

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  • Fully integrated analog filters using bipolar-JFET technology [active fifth order Chebyshev low-pass realisation]

    Publication Year: 1978 , Page(s): 814 - 821
    Cited by:  Patents (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1240 KB)  

    A new approach for realizing high-order analog filters which can be fully integrated using a compatible bipolar and ion-implanted JFET process is described. This approach is based on the recognition that what is really needed is a long time constant monolithic integrator which can be effectively realized in a small silicon area. These integrators have been designed, fabricated, and used in a `leap... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan