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IEEE Journal of Solid-State Circuits

Issue 6 • Date Dec. 1983

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Displaying Results 1 - 25 of 36
  • [Inside front cover - December 1983]

    Publication Year: 1983, Page(s): f2
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  • 1983 Index IEEE Journal of Solid-State Circuits Vol. SC-18

    Publication Year: 1983, Page(s):i1 - i13
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  • Table of contents (December 1983)

    Publication Year: 1983, Page(s):617 - 618
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  • Editor's Note (December 1983)

    Publication Year: 1983, Page(s): 619
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  • IEEE Solid-State Circuits Council Fellow Evaluations

    Publication Year: 1983, Page(s): 620
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  • IEEE Fellow Nomination Guidelines

    Publication Year: 1983, Page(s): 621
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  • Foreword (December 1983)

    Publication Year: 1983, Page(s):622 - 623
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  • An improved frequency compensation technique for CMOS operational amplifiers

    Publication Year: 1983, Page(s):629 - 633
    Cited by:  Papers (212)  |  Patents (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation f... View full abstract»

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  • A precision curvature-compensated CMOS bandgap reference

    Publication Year: 1983, Page(s):634 - 643
    Cited by:  Papers (127)  |  Patents (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1441 KB)

    A precision curvature-compensated switched-capacitor bandgap reference is described which uses a standard digital CMOS process and achieves temperature stability significantly lower than has previously been reported for CMOS circuits. The theoretically achievable temperature coefficient approaches 10 ppm//spl deg/C over the commercial temperature range and uses a straightforward room temperature t... View full abstract»

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  • A CMOS SLIC with an automatic balancing hybrid

    Publication Year: 1983, Page(s):678 - 684
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1147 KB)

    A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a... View full abstract»

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  • An integrated electronic telephone circuit

    Publication Year: 1983, Page(s):684 - 691
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (971 KB)

    An integrated electronic telephone circuit (ETC) providing all the necessary elements of a telephone station apparatus is described. The ETC includes a speech network, tone ringer, dual-tone multifrequency (DTMF) dialer and DC line interface circuit. A microprocessor port facilitates automatic dialing features under control of a separate microprocessor. The speech network and dialer circuits opera... View full abstract»

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  • A continuously variable slope adaptive delta modulation codec system

    Publication Year: 1983, Page(s):692 - 700
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (957 KB)

    The author describes a CMOS single-chip monolithic adaptive delta modulation coder/decoder (codec). The codec uses a 56 kHz sample rate and is implemented with novel switched-capacitor circuits. The simplicity and efficiency of the encoding/decoding scheme allows the inclusion of several other functions on the chip, including a dual-tone multifrequency generator and and an 8-step programmable atte... View full abstract»

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  • A CMOS switched-capacitor variable line equalizer

    Publication Year: 1983, Page(s):700 - 706
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (923 KB)

    The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order th... View full abstract»

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  • A monolithic conditioner for thermocouple signals

    Publication Year: 1983, Page(s):707 - 716
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1302 KB)

    The authors discusses a monolithic signal conditioner for direct thermocouple input which provides gain, common-mode signal rejection, and cold-junction compensation. It provides 50 to 1 ambient temperature rejection and a nominal 10 mV//spl deg/C output range. It operates on as little as 800 /spl mu/W, provides a thermocouple fault alarm and has provision for use as a set-point feedback controlle... View full abstract»

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  • A monolithic high-speed sample-and-hold amplifier for digital audio

    Publication Year: 1983, Page(s):716 - 722
    Cited by:  Papers (3)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (974 KB)

    A monolithic high-speed sample-and-hold amplifier is described which has an acquisition time of 1.5 /spl mu/s to 0.001% for a 10-V step and an aperture uncertainty of less than 0.5 ns. Distortion is 0.001% over the audio band, while in an A/D and D/A converter loop a signal-to-noise ratio better than 90 dB is measured. Chip size is 1.5/spl times/2.5 mm/SUP 2/. View full abstract»

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  • A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

    Publication Year: 1983, Page(s):723 - 729
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (935 KB)

    A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chi... View full abstract»

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  • A complete high-speed voltage output 16-bit monolithic DAC

    Publication Year: 1983, Page(s):729 - 735
    Cited by:  Papers (18)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1217 KB)

    A new single-chip 16-bit monolithic digital/analog converter (DAC) with on-chip voltage reference and operational amplifiers has achieved /spl plusmn/0.0015% linearity, 10 ppm//spl deg/C gain drift, and 4-/spl mu/s settling time. Novel elements of the 16-bit DAC include: the fast settling open-loop reference with a buried Zener, a fast-settling output operational amplifier without the use of feedf... View full abstract»

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  • A CCD time-integrating correlator

    Publication Year: 1983, Page(s):736 - 744
    Cited by:  Papers (6)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1768 KB)

    A CCD binary-analog time-integrating correlator has been designed and operated at 20 MHz clock rate. The 32-channel device is capable of integration periods in excess of 25 /spl mu/s or 500 clock periods, equivalent to a time-bandwidth product of 250. The device architecture is based on charge-domain signal processing for high-speed operation and does not required on-chip logic for storage of the ... View full abstract»

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  • A high-speed digitally programmable CCD transversal filter

    Publication Year: 1983, Page(s):745 - 753
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1186 KB)

    A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A... View full abstract»

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  • An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

    Publication Year: 1983, Page(s):753 - 761
    Cited by:  Papers (44)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1167 KB)

    A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a... View full abstract»

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  • A new internal overvoltage protection structure for the bipolar power transistor

    Publication Year: 1983, Page(s):773 - 777
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB)

    A new integrated structure for internal overvoltage protection of a bipolar power transistor is presented which consists of the simultaneous integration of an interdigitated n-p-n (p-n-p) bipolar power transistor and a merged n-(p) channel-enhancement MOSFET. The magnitude of the overvoltage protection for the bipolar transistor is determined by the threshold voltage of the merged MOSFET, which ca... View full abstract»

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  • A one-dimensional DC model for nonrectangular IGFETs

    Publication Year: 1983, Page(s):778 - 784
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (763 KB)

    The drain current of a nonrectangular IGFET operating in the triode and subthreshold regions is shown to be identical to that of a rectangular device of an appropriate effective aspect ratio. The effective aspect ratio can be calculated by conformal mapping techniques, or by two-dimensional numerical methods. Experimental results are presented demonstrating the scaling property for a variety of no... View full abstract»

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  • Analytical model and characterization of small-geometry buried-channel depletion MOSFETs

    Publication Year: 1983, Page(s):784 - 793
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1033 KB)

    Small-geometry buried-channel depletion MOSFETs (BCD-MOSFETs) are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity saturation effects. The drain current is calculated based on the surface electrons induced by the gate-bias voltage and the buried-channel junction FET. The narrow-channel effect is modeled not only by the additional depletio... View full abstract»

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  • Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

    Publication Year: 1983, Page(s):803 - 807
    Cited by:  Papers (104)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB)

    Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalen... View full abstract»

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  • A high performance 256K (512K) static ROM

    Publication Year: 1983, Page(s):807 - 810
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    A 256K ROM, fully expandable to 512K, has been fabricated. The ROM utilizes 2.5-/spl mu/m NMOS multiple threshold technology. It has a typical access time of 120 ns and uses push-pull circuitry to achieve an active current of 60 mA and a standby current of 1.9 mA. Total chip size is 39K mil/SUP 2/ for the 256K version. A modified X-cell has been chosen which requires 7.5 /spl mu/m. Current sensing... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan