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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1983

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Displaying Results 1 - 25 of 36
  • [Inside front cover - December 1983]

    Page(s): f2
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  • 1983 Index IEEE Journal of Solid-State Circuits Vol. SC-18

    Page(s): i1 - i13
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  • Table of contents (December 1983)

    Page(s): 617 - 618
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  • Editor's Note (December 1983)

    Page(s): 619
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  • IEEE Solid-State Circuits Council Fellow Evaluations

    Page(s): 620
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  • IEEE Fellow Nomination Guidelines

    Page(s): 621
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  • Foreword (December 1983)

    Page(s): 622 - 623
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  • An improved frequency compensation technique for CMOS operational amplifiers

    Page(s): 629 - 633
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    The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz. View full abstract»

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  • A precision curvature-compensated CMOS bandgap reference

    Page(s): 634 - 643
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    A precision curvature-compensated switched-capacitor bandgap reference is described which uses a standard digital CMOS process and achieves temperature stability significantly lower than has previously been reported for CMOS circuits. The theoretically achievable temperature coefficient approaches 10 ppm//spl deg/C over the commercial temperature range and uses a straightforward room temperature trim procedure. Experimental data from monolithic prototype samples are presented which are consistent with theoretical predictions. The experimental prototype circuit occupies 3500 mil/SUP 2/ and dissipates 12 mW with /spl plusmn/5 V power supplies. The proposed reference is believed to be suited for use in monolithic data acquisition systems with resolutions of 10 to 12 bits. View full abstract»

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  • A CMOS SLIC with an automatic balancing hybrid

    Page(s): 678 - 684
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    A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL. View full abstract»

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  • An integrated electronic telephone circuit

    Page(s): 684 - 691
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    An integrated electronic telephone circuit (ETC) providing all the necessary elements of a telephone station apparatus is described. The ETC includes a speech network, tone ringer, dual-tone multifrequency (DTMF) dialer and DC line interface circuit. A microprocessor port facilitates automatic dialing features under control of a separate microprocessor. The speech network and dialer circuits operate with instantaneous input voltage as low as 1.4 V. The DTMF generator incorporates a high-precision frequency synthesis technique. Because of the reduction of frequency errors, an inexpensive ceramic resonator can be used as the frequency reference for the dialer. A linear/I/SUP 2/L process with two-layer metal interconnects is used to fabricate the 125/spl times/146 mil ETC die. View full abstract»

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  • A continuously variable slope adaptive delta modulation codec system

    Page(s): 692 - 700
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    The author describes a CMOS single-chip monolithic adaptive delta modulation coder/decoder (codec). The codec uses a 56 kHz sample rate and is implemented with novel switched-capacitor circuits. The simplicity and efficiency of the encoding/decoding scheme allows the inclusion of several other functions on the chip, including a dual-tone multifrequency generator and and an 8-step programmable attenuator. These features make it especially suitable for private automatic branch exchange (PABX) applications. Experimental results are presented that show the circuit meets the necessary systems requirement for all usual applications. View full abstract»

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  • A CMOS switched-capacitor variable line equalizer

    Page(s): 700 - 706
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    The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter. View full abstract»

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  • A monolithic conditioner for thermocouple signals

    Page(s): 707 - 716
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    The authors discusses a monolithic signal conditioner for direct thermocouple input which provides gain, common-mode signal rejection, and cold-junction compensation. It provides 50 to 1 ambient temperature rejection and a nominal 10 mV//spl deg/C output range. It operates on as little as 800 /spl mu/W, provides a thermocouple fault alarm and has provision for use as a set-point feedback controller as well as for signal measurements. The circuit is fabricated on a standard linear IC process and uses laser-wafer-trimmed thin-film resistors to achieve 1/spl deg/C temperature calibration. View full abstract»

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  • A monolithic high-speed sample-and-hold amplifier for digital audio

    Page(s): 716 - 722
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    A monolithic high-speed sample-and-hold amplifier is described which has an acquisition time of 1.5 /spl mu/s to 0.001% for a 10-V step and an aperture uncertainty of less than 0.5 ns. Distortion is 0.001% over the audio band, while in an A/D and D/A converter loop a signal-to-noise ratio better than 90 dB is measured. Chip size is 1.5/spl times/2.5 mm/SUP 2/. View full abstract»

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  • A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

    Page(s): 723 - 729
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    A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chip by using an advanced nitride self-aligned (advanced-NSA) process. View full abstract»

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  • A complete high-speed voltage output 16-bit monolithic DAC

    Page(s): 729 - 735
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    A new single-chip 16-bit monolithic digital/analog converter (DAC) with on-chip voltage reference and operational amplifiers has achieved /spl plusmn/0.0015% linearity, 10 ppm//spl deg/C gain drift, and 4-/spl mu/s settling time. Novel elements of the 16-bit DAC include: the fast settling open-loop reference with a buried Zener, a fast-settling output operational amplifier without the use of feedforward compensation, and a modified R-2R ladder network. Thermal considerations played a significant role in the design. The DAC is fabricated using a 20-V process to reduce device sizes and therefore die size. All laser trimming including temperature drift compensation is performed at the wafer level. The converter does not require external components for operation. View full abstract»

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  • A CCD time-integrating correlator

    Page(s): 736 - 744
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    A CCD binary-analog time-integrating correlator has been designed and operated at 20 MHz clock rate. The 32-channel device is capable of integration periods in excess of 25 /spl mu/s or 500 clock periods, equivalent to a time-bandwidth product of 250. The device architecture is based on charge-domain signal processing for high-speed operation and does not required on-chip logic for storage of the binary reference. The device is tailored for weak signal applications, and a new charge skimming circuit has been devised which allows the small portion of the integrated charge containing the correlation function to be separated from the large register by tenfold. The correlator has a stationary pattern noise which can be eliminated with simple postprocessing, yielding a dynamic range of 67 dB. View full abstract»

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  • A high-speed digitally programmable CCD transversal filter

    Page(s): 745 - 753
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    A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible. View full abstract»

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  • An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

    Page(s): 753 - 761
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    A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz. View full abstract»

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  • A new internal overvoltage protection structure for the bipolar power transistor

    Page(s): 773 - 777
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    A new integrated structure for internal overvoltage protection of a bipolar power transistor is presented which consists of the simultaneous integration of an interdigitated n-p-n (p-n-p) bipolar power transistor and a merged n-(p) channel-enhancement MOSFET. The magnitude of the overvoltage protection for the bipolar transistor is determined by the threshold voltage of the merged MOSFET, which can be controlled by the thickness of the gate oxide and the substrate doping of the merged MOSFET. A simple analytical model for the overvoltage protection has been developed. The fabrication techniques and design considerations of this integrated structure are discussed, and the applicability of the proposed structure is demonstrated experimentally. View full abstract»

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  • A one-dimensional DC model for nonrectangular IGFETs

    Page(s): 778 - 784
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    The drain current of a nonrectangular IGFET operating in the triode and subthreshold regions is shown to be identical to that of a rectangular device of an appropriate effective aspect ratio. The effective aspect ratio can be calculated by conformal mapping techniques, or by two-dimensional numerical methods. Experimental results are presented demonstrating the scaling property for a variety of nonrectangular IGFET configurations. The theory developed is then used to derive an equivalent circuit for IGFETs having more than one source or drain. An approximate analysis is performed which results in an expression for the increase in drain current of a bent IGFET in the saturation region. View full abstract»

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  • Analytical model and characterization of small-geometry buried-channel depletion MOSFETs

    Page(s): 784 - 793
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    Small-geometry buried-channel depletion MOSFETs (BCD-MOSFETs) are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity saturation effects. The drain current is calculated based on the surface electrons induced by the gate-bias voltage and the buried-channel junction FET. The narrow-channel effect is modeled not only by the additional depletion-layer charges created by a fringing-field effect in the field region, but also by the effective channel width as a function of gate-bias voltage. Surface-electron mobility is modeled as a function of the vertical and lateral electrical fields created by the gate-bias and drain voltages, while bulk-electron mobility is described as a function of the lateral electric field due to the drain voltage. Theoretical results on drain current are in good agreement with experimental results. View full abstract»

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  • Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

    Page(s): 803 - 807
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    Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method for computer simulation is discussed. View full abstract»

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  • A high performance 256K (512K) static ROM

    Page(s): 807 - 810
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    A 256K ROM, fully expandable to 512K, has been fabricated. The ROM utilizes 2.5-/spl mu/m NMOS multiple threshold technology. It has a typical access time of 120 ns and uses push-pull circuitry to achieve an active current of 60 mA and a standby current of 1.9 mA. Total chip size is 39K mil/SUP 2/ for the 256K version. A modified X-cell has been chosen which requires 7.5 /spl mu/m. Current sensing was chosen to optimize access time. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan