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Solid-State Circuits, IEEE Journal of

Issue 5 • Date Oct. 1983

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Displaying Results 1 - 25 of 34
  • [Inside front cover - October 1983]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (October 1983)

    Page(s): 433 - 434
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    Freely Available from IEEE
  • Foreword (October 1983)

    Page(s): 435 - 436
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    Freely Available from IEEE
  • A 90 ns 256K x 1 bit DRAM with double-level Al technology

    Page(s): 437 - 440
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    A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques. View full abstract»

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  • A low-power sub 100 ns 256K bit dynamic RAM

    Page(s): 441 - 446
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    A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement. View full abstract»

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  • A 64K DRAM with 35 ns static column operation

    Page(s): 447 - 451
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    A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP. View full abstract»

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  • A sub-100 ns 256K DRAM with open bit line scheme

    Page(s): 452 - 456
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    A 256K DRAM with a 34.1 mm/SUP 2/ die size and a typical access time of 70 ns has been fabricated by using a newly designed boosted high-level clock generator circuit and triple poly-Si processing. For two-cell array configurations and sensing schemes, the available signal and uncommon mode noise levels at the input terminal of the sense amplifiers were studied. It was concluded that the open bit line configuration was the better one for a high-speed 256 kbit DRAM with a small die size, and the device characteristics obtained confirmed this approach. The device can operate in the nibble mode with a 15-ns access time from a CAS clock and can be refreshed with CAS before RAS automatic refresh mode. The yield has been enhanced with optimized redundancy. View full abstract»

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  • A 70 ns high density 64K CMOS dynamic RAM

    Page(s): 457 - 463
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    A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application. View full abstract»

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  • A 256K dynamic RAM with page-nibble mode

    Page(s): 470 - 478
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    A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved. View full abstract»

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  • A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

    Page(s): 479 - 485
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    This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time. View full abstract»

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  • A 25 ns 8K x 8 static MTL/I/sup 2/L RAM

    Page(s): 486 - 494
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    An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure. View full abstract»

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  • A battery backup 64K CMOS RAM with double-level aluminum technology

    Page(s): 494 - 498
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    A full CMOS 8K /spl times/ 8 bit RAM has been developed, incorporating a new circuit to transfer the memory automatically to the data-retention mode when supply voltage is lowered. For reducing operating power dissipation, internally synchronous circuits and a split power control technique were employed. A minimum cell size was obtained through the use of a double-level aluminum process. View full abstract»

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  • A 35 ns 2K x 8 HMOS static RAM

    Page(s): 498 - 508
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    This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/. View full abstract»

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  • A high speed 16 kbit ECL RAM

    Page(s): 509 - 514
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    A 16384 /spl times/ 1 bit ECL RAM (emitter coupled logic random access memory) with an access time of 15 ns and a power dissipation of 700 mW has been developed. The high packing density and performance were achieved by using a p-n-p load cell, a novel ECL circuit, and U-groove isolation. The test results proved that a p-n-p load cell is very effective in producing a fast high-density bipolar RAM having a capacity of over 64 Kbits. View full abstract»

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  • A 4.5 ns access time 1K x 4 bit ECL RAM

    Page(s): 515 - 520
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    An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT. View full abstract»

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  • A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

    Page(s): 520 - 524
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    This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout. View full abstract»

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  • Control logic and cell design for a 4K NVRAM

    Page(s): 525 - 532
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    A high-density 4K 5-V-only nonvolatile static RAM has been designed using a wafer stepper HMOS I FLOTOX E/SUP 2/PROM technology. Normal SRAM read/write operations and parallel data transfer between SRAM and E/SUP 2/PROM array are possible. On-chip high-voltage regulation and generation, junction leakage control, and self-timing circuitry ensure full military temperature operation. Power-down store lockout protection and power-up automatic recall are featured. View full abstract»

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  • High-voltage regulation and process considerations for high-density 5 V-only E/sup 2/PROM's

    Page(s): 532 - 538
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    A high density 5-V-only HMOS 1 FLOTOX E/SUP 2/PROM technology has been developed using stepper lithography and dry etching techniques. A 1.5-/spl mu/m minimum feature size and 0.5-/spl mu/m registration result in a FLOTOX cell with an area of 270 /spl mu/m/SUP 2/. This represents a 50% reduction of the original cell size. Equivalent endurance (10K cycles) and data retention (10 years) have been obtained. Improved critical dimension control has increased the uniformity of the new cell within the array. Junction leakage has been reduced by using an extended low-temperature anneal cycle. Circuit techniques have been developed to ensure full temperature range (-55-125/spl deg/C) operation. A capacitive voltage divider in a feedback loop, an E/SUP 2/ trimmable voltage reference, and a switched-capacitor RC network are employed to produce a temperature-stable programming pulse with a rising edge time constant of ~ 600 /spl mu/s. The programming voltage can be trimmed with an accuracy of /spl plusmn/ 0.5 V over a typical range of 19-24 V in order to match the requirements of the array. 16K and 64K 5-V-only E/SUP 2/PROMs with die sizes of 128 /spl times/ 182 mil and 223 X 278 mil have been fabricated. View full abstract»

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  • A 16 kbit smart 5 V-only EEPROM with redundancy

    Page(s): 539 - 544
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    This paper describes several circuit techniques used in the design of a 5-V-only 16 Kbit EEPROM. The EEPROM uses a two transistor cell based on Fowler-Nordheim tunneling to a floating polysilicon gate. The EEPROM features 5-V-only operation, a self-timed program cycle with automatic erase before write, address and data latches, and a `ready' line output. These features make the program cycle timing compatible with static RAMs and simplifies the microprocessor interface. A new redundancy technique using EE cells as the programming element is also described. View full abstract»

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  • A 288K CMOS EPROM with redundancy

    Page(s): 544 - 550
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    A 150 ns 288K CMOS EPROM with a nine-block cell array and a standby current of less than 1 /spl mu/A has been developed. This device can be used as an 8 or 9-bit EPROM. The ninth block can be used as a redundant block by electrically programmable polysilicon fuses. A redundant row decoder is also included. Improvements in the lithography and process technologies have reduced the cell size to 9 /spl times/ 6 /spl mu/m and the chip size to 7.44 /spl times/ 4.65 mm. View full abstract»

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  • A 16K E/SUP 2/PROM using E/SUP 2/ element redundancy

    Page(s): 550 - 553
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    A new LSI memory redundancy technique using E/SUP 2/PROM cells as the programmable element has been developed. Yield enhancement with this technique has been demonstrated using two redundant rows on a 16K E/SUP 2/PROM chip. This paper describes the structure and operation of the circuit blocks used, and how these circuits interface with the memory chip to produce the observed yield enhancement. The method for programming the redundancy elements is described, along with circuit advantages and capabilities unique to E/SUP 2/PROM redundancy. Device performance and yield enhancement for the 16K E/SUP 2/PROM are summarized. View full abstract»

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  • A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

    Page(s): 554 - 561
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    A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening. View full abstract»

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  • A 16K CMOS PROM with polysilicon fusible links

    Page(s): 562 - 567
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    A 16K synchronous CMOS PROM with polysilicon fusible links and a 2K-word by 8-bit organization is described. The memory cell makes use of the vertical bipolar NPN that is inherent in the p-well CMOS process. An advanced polysilicon fuse process is used for the fusible links. The technology incorporates use of an epitaxial layer that eliminates latchup potential at programming voltages. A special verify mode is used to detect marginally blown fuses during programming. The design features a typical access time of 50 ns and 1-/spl mu/A standby current. View full abstract»

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  • A multiplexed 4 Mbit bubble memory device

    Page(s): 567 - 571
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    A 4-Mbit magnetic bubble memory has been designed and demonstrated which is architecturally compatible with an 1-Mbit memory. The design goals for the memory were to achieve user software compatibility and pin-for-pin interchangeability. To achieve this, one key 4-Mbit device feature was additional multiplexing. This was obtained by a novel application of thin-film detectors and replicate generators along with other function designs. The result is a 4 bit/cycle write and read operation and a page length of 512 bits. The margins for the functions are shown to be comparable to those for the 1-Mbit process while the detector signal is over three times larger. The 1-Mbit process is extended to the 4-Mbit device by adding a thin permalloy level which requires one additional critical alignment and scaling geometries to give a 0.75-/spl mu/m minimum feature size on a 5.5-/spl mu/m square memory cell. View full abstract»

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  • A 20K-gate CMOS gate array

    Page(s): 578 - 584
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    Combining an advanced 2-/spl mu/m CMOS technology with a newly developed triple-level metallization technology, a high-performance 20K-gate CMOS gate array has been developed. The advantage of triple-level metallization for area saving in a large-scale gate array was evaluated by a computer simulation. The typical gate delay is 1.5 ns with fan-out of 3, and 3-mm metal interconnect length. As a test vehicle for verifying the high-performance gate array, a 32/spl times/32-bit parallel multiplier has been successfully designed and fabricated. Cell utilization is about 65%. A typical multiplication takes 120 ns at a 5-MHz clock rate, with a power dissipation of 400 mW. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan