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IEEE Journal of Solid-State Circuits

Issue 4 • Aug. 1983

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Displaying Results 1 - 14 of 14
  • [Inside front cover - August 1983]

    Publication Year: 1983, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1983)

    Publication Year: 1983, Page(s): 377
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  • A digitally programmable switched-capacitor universal active filter/oscillator

    Publication Year: 1983, Page(s):383 - 389
    Cited by:  Papers (24)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    A universal second-order switched-capacitor filter section has been fabricated on an NMOS chip. The device can perform all five basic filter types as well as a sine wave oscillator without external components, while requiring only an external clock. The filter type is determined by selecting one or more of three input pins. The filter response is determined by ten external programming pins which m... View full abstract»

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  • A macromodel for integrated all-MOS operational amplifiers

    Publication Year: 1983, Page(s):389 - 394
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (846 KB)

    A macromodel for integrated all-MOS operational amplifiers is developed with reference to circuits where the settling behavior of the op amps is of particular concern. Expressions for the values of the elements of the macromodel are obtained from typical measured characteristics. It is shown that the proposed macromodel can satisfactorily predict both small-signal and large-signal behavior of the ... View full abstract»

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  • GaAs integrated circuits for error-rate measurement in high-speed digital transmission systems

    Publication Year: 1983, Page(s):402 - 408
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1517 KB)

    A high-speed GaAs MSI PRBS generator and an error detector have been built, tested, and applied to bit-error ratio measurements in a fiber-optic transmission link. The generator produces a 1023 bit sequence at 2 Gbit/s data rate. The detector compares, bit-by-bit, the input data with a locally regenerated sequence. With a 2 GHz clock, the direct-coupled generator/detector combination, without an o... View full abstract»

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  • A new diagnostic test for operating margin problems in LSI memory

    Publication Year: 1983, Page(s):409 - 413
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (753 KB)

    A new diagnostic test technique for operating margin problems in LSI memory has been developed that makes it possible to distinguish the failed circuit block exactly even if plural failed blocks exist. This method consists of two techniques using a newly developed time domain method (TDM). One is a technique that divides the multiple failure due to the plural failed circuit blocks into single fail... View full abstract»

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  • Approximation of wiring delay in MOSFET LSI

    Publication Year: 1983, Page(s):418 - 426
    Cited by:  Papers (273)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1229 KB)

    Two approximation methods for wiring delay in MOS LSI are studied. One is analytical and the other is a lumped circuit approximation. The basic model for wiring is a distributed CR line with a drive MOSFET at one end and a capacitive load at the other end. Simple approximated formulas for the delay and the step response of this model are obtained. Approximation of a distributed CR line by lumped R... View full abstract»

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  • A CMOS magnetic field sensor

    Publication Year: 1983, Page(s):426 - 428
    Cited by:  Papers (39)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    The authors present a novel, fully integrated magnetic field sensor made in the standard, polysilicon-gate CMOS technology. The circuit shows a sensitivity of 1.2 V/T with 10 V supply voltage and 100 /spl mu/A current consumption. The circuit consists of a pair of split-drain MOS transistors in a CMOS-differential amplifier-like configuration. View full abstract»

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  • An effect of the subthreshold current on scaled-down MOS dynamic RAMs

    Publication Year: 1983, Page(s):429 - 431
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Data-output holding characteristics of MOS dynamic RAMs with 2.5 /spl mu/m design rules are studied by employing the hidden-RAS-only-refresh mode. It is verified that the noise voltage caused by internal circuit operation increases the subthreshold current and that the clamp circuitry effectively decreases the subthreshold current. View full abstract»

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  • [Back inside cover - August 1983]

    Publication Year: 1983, Page(s): b1
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    Freely Available from IEEE
  • Design, fabrication, and performance of scaled analog ICs

    Publication Year: 1983, Page(s):395 - 402
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1472 KB)

    This paper concerns scaled MOS circuits for high-speed and high-density analog LSIs. The effect of scaling the devices employing three different scaling laws (constant electric field, constant voltage, and quasiconstant voltage laws) is examined using both the first-order approximation and two-dimensional device simulator. Versatile scaling relationships for analog circuits are then developed. The... View full abstract»

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  • On the feasibility of an erasable programmable, read-only memory (EPROM) based on Josephson technology

    Publication Year: 1983, Page(s):428 - 429
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Experimental results on optically controllable Josephson junctions are reported. The unique features of such structures are discussed in the framework of a memory cell recently proposed by Faris. View full abstract»

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  • Design consideration of a static memory cell

    Publication Year: 1983, Page(s):414 - 418
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    Describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a DC stability factor introduced from transfer curves of the inverters in the cell. The criteria use only static conditions for read/write/retain operations. The designed cell, considering mask-misalignment, measured 22.8×27.6 ... View full abstract»

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  • Integrated switched-capacitor FDNR filter

    Publication Year: 1983, Page(s):378 - 383
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    A switched-capacitor filter using a frequency-dependent negative resistance (FDNR) is described. FDNR filters closely simulate passive LC filters, thereby retaining passband stability and design simplicity. The filter has been implemented in LSI and designed to perform the transmit/receive filtering for PCM codecs. Circuits are described that overcome the floating node and floating amplifier probl... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com