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IEEE Journal of Solid-State Circuits

Issue 3 • June 1983

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Displaying Results 1 - 25 of 26
  • [Inside front cover - June 1983]

    Publication Year: 1983, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1983)

    Publication Year: 1983, Page(s): 233
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    Freely Available from IEEE
  • Foreword: Special Issue on the Eighth European Solid-State Circuits Conference

    Publication Year: 1983, Page(s):234 - 235
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    Freely Available from IEEE
  • A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

    Publication Year: 1983, Page(s):245 - 249
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (671 KB)

    Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Opera... View full abstract»

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  • A 24-bit microprocessor for data communication systems designed on the basis of a general cell library

    Publication Year: 1983, Page(s):250 - 261
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    A 24-bit microprogrammed processor with 200 ns instruction cycle time has been realized as an experimental special purpose VLSI chip. The design was based on a general cell library and a set of advanced CAD tools. The technology used is a 3 /spl mu/m silicon gate, n-channel, single metallization MYMOS process. The chip integrates 9400 gate functions plus a 256/spl times/27 bit static RAM on 78.5 m... View full abstract»

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  • A versatile CMOS rate multiplier/variable divider

    Publication Year: 1983, Page(s):267 - 272
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB)

    A versatile integrated circuit that delivers an optimally spaced output signal is presented. The paper includes a comparison of the commonly used rate-multiplication scheme and the accumulator rate-multiplier principle. It is shown that this principle always delivers the best possible digital approximation of a regular signal, but it is inherently slower. The design considerations for speed improv... View full abstract»

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  • MOS transistors operated in the lateral bipolar mode and their application in CMOS technology

    Publication Year: 1983, Page(s):273 - 279
    Cited by:  Papers (150)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (781 KB)

    Operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively. It yields a good bipolar transistor that is fully compatible with any bulk CMOS technology. Experimental results show that high /spl beta/-gain can be achieved and that matching and 1/f noise properties are much better than in MOS operation. Examples of experimental circuits in CMOS technology illustrate t... View full abstract»

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  • An integrated binary correlator module

    Publication Year: 1983, Page(s):286 - 290
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    A correlator module using the pseudorandom comparison (PRC) algorithm has been designed and fabricated in a standard 8 /spl mu/m PMOS process. It demonstrates the validity of the principle and the feasibility of a low-cost integrated correlator or RMS meter based on it. The chip runs at a sampling rate of 500 kHz, dissipates 90 mW, and its size is 2.4 mm/SUP 2/ not including the delay element whic... View full abstract»

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  • A monolithic adaptive filter

    Publication Year: 1983, Page(s):291 - 296
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (881 KB)

    Reports a monolithic adaptive filter which has been realized using purely analog sampled-data MOS and CCD techniques. The filter implements a full Widrow least mean-squares algorithm over 65 data points. Central to this design is a novel, compact analog multiplier/accumulator circuit, which is presented in detail. The 65-point adaptive filter, which is cascadable, dissipates 200 mW from a 15 V sup... View full abstract»

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  • A 14-bit monotonic NMOS D/A converter

    Publication Year: 1983, Page(s):297 - 301
    Cited by:  Papers (8)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (759 KB)

    A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip. The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal. The small chip size of about 8.5 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution cont... View full abstract»

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  • A 12-bit monolithic 70 ns DAC

    Publication Year: 1983, Page(s):302 - 305
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (722 KB)

    Describes a 12-bit monolithic digital-to-analog converter with 70 ns settling time and a low output glitch content. The device is fabricated on a standard high speed digital process and needs no post-processing trimming to achieve the required accuracy and monotonicity. The output from this device is in the form of two complementary output currents, which may be terminated in resistive loads or am... View full abstract»

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  • A wide-band limiting amplifier for optical fiber repeaters

    Publication Year: 1983, Page(s):333 - 340
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    An integrated amplifier having a bandwidth of 470 MHz, and a gain and limiting range of 60 dB has been realized using a cascade of three cells on an uncommitted array. The circuit is capable of operating in optical fiber repeaters in the signal or retiming path at transmission rates up to 650 MBd. Direct expressions for calculating the gain and bandwidth have been derived which allow optimization ... View full abstract»

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  • A 256 kbit ROM with serial ROM cell structure

    Publication Year: 1983, Page(s):340 - 344
    Cited by:  Papers (1)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (775 KB)

    The realization of a 256 kbit ROM using a 500 /spl Aring/ E/D NMOS technology is described. A high packaging density has been achieved by using a NAND structure in the memory array and in the decoders. Some characteristics of this serial ROM structure are discussed and compared with the conventional parallel configurations. The 32K/spl times/8 bit ROM with a bit size of 5.25/spl times/5.5 /spl mu/... View full abstract»

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  • A single-chip self-contained speech recognizer

    Publication Year: 1983, Page(s):344 - 349
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    A fully integrated speech recognition LSI has been developed. The speech recognition LSI can recognize a speaker-dependent vocabulary of about 200 isolated words with high accuracy in real time, using several memories, which are a phoneme template memory, word dictionary memory, and work memory. This LSI is designed to perform the total speech recognition processing, including the endpoint detecti... View full abstract»

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  • A 3 /spl mu/m NMOS high-performance LPC speech synthesizer chip

    Publication Year: 1983, Page(s):349 - 359
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1142 KB)

    A high performance speech processing integrated circuit (SPIC) based on linear predictive coding (LPC) techniques is presented. Both system and technological aspects of the SPCI design are covered in detail. The SPIC synthesizer chip will normally be used in a three-chip minimum system configuration including the synthesizer, a microcomputer, and an external vocabulary ROM. The speech quality can ... View full abstract»

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  • A high speed GaAs 8-bit multiplexer using capacitor-coupled logic

    Publication Year: 1983, Page(s):359 - 364
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1103 KB)

    Capacitor-coupled logic has been used to design and fabricate a GaAs eight channel multiplexer IC for use at 1.2 Gbit/s, which is fully compatible with ECL, and which offers good stability and very high tolerances to device parameters and circuit voltages. A technique has been developed to enable initial charging of all the coupling capacitors, upon application of a simple pulse sequence to contro... View full abstract»

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  • A GaAs low-power normally-on 4-bit ripple carry adder

    Publication Year: 1983, Page(s):365 - 369
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (857 KB)

    The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of ... View full abstract»

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  • Correction to "A Compact, Flexible LPC Vocoder Based on a Commercial Signal Processing Microcomputer"

    Publication Year: 1983, Page(s): 376
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (131 KB)

    First Page of the Article
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  • [Back inside cover - June 1983]

    Publication Year: 1983, Page(s): b1
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    Freely Available from IEEE
  • Digital signal processing for video applications

    Publication Year: 1983, Page(s):280 - 285
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1496 KB)

    Digital video signal processing is one result of the fast progress in NMOS-VLSI techniques. The attractions of using digital data processing methods in an analog application field are the availability of CAD tools for the design of digital ICs and the integration of digital filter functions. Besides the key components such as microcomputers, A/D, and D/A converters, the digital filter techniques a... View full abstract»

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  • GaAs digital dynamic ICs for applications up to 10 Ghz

    Publication Year: 1983, Page(s):369 - 376
    Cited by:  Papers (24)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    To evaluate the potentiality of GaAs MESFETs as transmitting gates, dynamic TT~ flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplificati... View full abstract»

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  • Microcomputers: trends, technologies, and design strategies

    Publication Year: 1983, Page(s):236 - 244
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2552 KB)

    Performance/cost ratios greater than 1 MIP per central processing unit (CPU) $ will be realized. As design rules decrease, the traditional superiority of on-chip interconnections increases, transistor performance becomes ever less an issue, and single-chip microcomputers will dominate the whole computer industry. CMOS technology will take the lead for the foreseeable future because its low power d... View full abstract»

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  • Compact NMOS building blocks and a methodology for dedicated digital filter applications

    Publication Year: 1983, Page(s):306 - 316
    Cited by:  Papers (27)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1400 KB)

    Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 μm NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 &... View full abstract»

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  • NORA: a racefree dynamic CMOS technique for pipelined logic structures

    Publication Year: 1983, Page(s):261 - 266
    Cited by:  Papers (192)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks φ and φ~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NO... View full abstract»

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  • Monolithic 70 V bipolar line driver IC for PCM SLIC

    Publication Year: 1983, Page(s):316 - 324
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    Describes a monolithic 70 V IC which is an integral part of a PCM subscriber line interface circuit (SLIC). A special design allows the realization of a line driving operational amplifier with stringent requirements on power drive, consumption, output overload protection and breakdown voltage. Other special SLIC functions are also implemented. Experimental results demonstrate the performance of th... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com