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IEEE Journal of Solid-State Circuits

Issue 1 • Date Feb. 1983

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Displaying Results 1 - 22 of 22
  • [Inside front cover - February 1983]

    Publication Year: 1983, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (February 1983)

    Publication Year: 1983, Page(s): 1
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    Freely Available from IEEE
  • Foreword (February 1983)

    Publication Year: 1983, Page(s):2 - 3
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    Freely Available from IEEE
  • A Compact, Flexible LPC Vocoder Based on a Commercial Signal Processing Microcomputer

    Publication Year: 1983, Page(s):4 - 9
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1097 KB)

    A very small, flexible, high-quality, full-duplex 2.4-kbit/s linear predictive vocoder has been implemented with commercially available integrated circuits. This fully digital realization is based on a distributed signal processing architecture employing three Nippon Electric Company (NEC) µPD7720 signal processing interface (SPI) single-chip microcomputers. One SPI implements the LPC analyze... View full abstract»

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  • A Family of Special Purpose Microprogrammable Digital Signal Processor IC's in an LPC Vocoder System

    Publication Year: 1983, Page(s):25 - 33
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1570 KB)

    This paper discusses a family of digital signal processor integrated circuits designed to be the fundamental buitding blocks of an LPC vocoder, specifically LPC analysis, AMDF pitch extraction, and LPC synthesis. The IC's are custom designs intended to minimize silicon real estate for extremely high performance, novel DSP architectures, and high computational demand algorithms. Each IC shares a co... View full abstract»

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  • A Single-Chip ADM LSI CODEC

    Publication Year: 1983, Page(s):33 - 39
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1099 KB)

    This paper describes the circuit design of an ADM (adaptive delta modulation) LSI CODEC with filters. The LSI chip is mounted in a 16-pin DIP and can operate with single low voltage supply. In order to realize a low power dissipation LSI IC, switched capacitor technology was used in the design of input/output filters and integrators, and C-array D/A converters and low voltage analog circuits were ... View full abstract»

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  • A Monolithic Audio Spectrum Analyzer

    Publication Year: 1983, Page(s):40 - 45
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (943 KB)

    A monolithic audio spectrum analyzer with 16 channels of bandpass filters, half-wave rectifiers, and postfiltering has been fabricated with double-poly NMOS technology. The chip was designed using switched-capacitor filter techniques. It performs a total of 84 poles of filtering and contains 100 operational amplifiers in an area of 225 X 280 mils. A system dynamic range of better than 43 dB, linea... View full abstract»

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  • A Switched-Capacitor Adaptive Lattice Filter

    Publication Year: 1983, Page(s):46 - 56
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1903 KB)

    Integration of an adaptive lattice filter in MOS-LSI technology is described. The architecture is designed to optimally exploit the advantages of analog and digital approaches. Switched-capacitor techniques are used for filtering and digital circuitry is used to perform the adaption. To test the concept, the analog circuitry was fabricated as an IC and operated with discrete digital circuitry. How... View full abstract»

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  • A Monolithic Data Acquisition Channel

    Publication Year: 1983, Page(s):57 - 65
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1635 KB)

    A monolithic data acquisition channel has been fabricated using a double level polysilicon NMOS process. The channel consists of a switched-capacitor filter, a continuous-time active RC filter, and a successive approximation analog-to digital converter. The IC is in the form of a parts kit for a data acquisition channel so that each functional component can be characterized independently. Stitch b... View full abstract»

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  • A Single Chip Speech Synthesizer Using a Switched-Capacitor Multiplier

    Publication Year: 1983, Page(s):65 - 75
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1596 KB)

    A single chip speech synthesizer was designed using a switched-capacitor multiplier to implement the LPC algorithm. The chip contains the LPC-10 filter, 20 kbit ROM, all control logic, a three-pole switched-capacitor low-pass filter, and an audio amplifier capable of driving a speaker directly. The chip was fabricated in 5 µm CMOS technology and is 218 mils on the side. View full abstract»

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  • An Integrated Voice Recognition System

    Publication Year: 1983, Page(s):75 - 81
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1199 KB)

    A low-cost recognition system for isolated words and small vocabulary (typically 15 words) is described. The main features of the system are: possibility of integration in a stand-alone small-size CMOS chip, very-low-power consumption (typically 200 µW at 3 V supply voltage), and automatic adaptation to the speaker without any tedious training mode. View full abstract»

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  • C/sup 2/MOS Speech Synthesis Systems

    Publication Year: 1983, Page(s):81 - 86
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    Employing an updated C/sup 2/MOS technique, two types of speech synthesizer LSI circuits, based on the PARCOR and the ADM methods, are introduced and described. These two LSI circuits fabricated with a standard metal gate CMOS process, have several features. 1) They can be operated with a single power supply over a 3-7 V range. 2) Their power dissipations are, respectively, 0.6 mW (PARCOR) and 0.1... View full abstract»

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  • A Single CMOS Speech Synthesis Chip and New Synthesis Techniques

    Publication Year: 1983, Page(s):87 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    A single CMOS speech synthesis LSI, organized as a special purpose microcomputer containing program ROM, RAM, 32K of speech data ROM, and a D/A converter is described in this paper. The chip utilizes new speech synthesis techniques to generate high quality speech, reproducing the natural inflection and intonation of the speaker, and has been used to produce speech at a bit rate of about 3 kbits/s. View full abstract»

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  • A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

    Publication Year: 1983, Page(s):91 - 99
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1665 KB)

    A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 ... View full abstract»

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  • An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation

    Publication Year: 1983, Page(s):128 - 138
    Cited by:  Papers (78)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1328 KB)

    MOSFET capacitor models implemented in circuit simulators currently do not guarantee charge conservation, which is extremely crucial for the simulation of dynamic RAM's, switched capacitor filters, and other MOS VLSI circuits. Several MOSFET capacitor models have been introduced in the literature; however, none of these models addresses the actual reasons of charge nonconservation in SPICE2. This ... View full abstract»

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  • [Back inside cover - February 1983]

    Publication Year: 1983, Page(s): b1
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    Freely Available from IEEE
  • Low Power 1 GHz Frequency Synthesizer LSI's

    Publication Year: 1983, Page(s):115 - 121
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    To realize a low-power low-cost highly-reliable frequency synthesizer for a 1 GHz band radio, a bipolar presealer IC, and a CMOS LSI, consisting of a programmable counter, phase frequency comparator, and fixed divider, have been developed. The PLL synthesizer principle, using a pulse swallow counter, has been adopted for 1 GHz direct programmable count down. Adopting an advanced bipolar process an... View full abstract»

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  • Modeling the Early Effect in Bipolar Transistors

    Publication Year: 1983, Page(s):139 - 140
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    For convenience in dc and small-signal low-frequency calculations, the effect of base width modulation (Early effect) on a bi-polar transistor- operating under low-level injection conditions in the forward-active mode--cans be taken into account by the use of a multiplying factor that is exponentially dependent on collector-base voltage. View full abstract»

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  • Impact of Scaling on MOS Analog Performance

    Publication Year: 1983, Page(s):106 - 114
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1448 KB)

    A first-order analysis of the impact of scaling on MOS analog performance under moderate scaling conditions is presented in this paper. Assuming a polysilicon gate ion-implanted MOS technology, quasi-constant voltage (QCV) scaling is shown to be the optimal scaling law, offering the best overall analog performance and resulting in an increase in functional density, gain-bandwidth product with a mo... View full abstract»

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  • Ultrafast Feedback A/D Conversion Made Possible by a Nonuniform Error Quantizer

    Publication Year: 1983, Page(s):99 - 105
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB)

    The paper presents a means of increasing the speed of a tracking (feedback) A/D converter by replacing the single comparator with an error quantizer having exponentially spaced representative levels. The technique is particularly suited to digitizing the class of signals which exhibit a large covariance between temporally adjacent samples. An n bit converter realized in this way incorporates a qua... View full abstract»

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  • Low-Power High-Drive CMOS Operational Amplifiers

    Publication Year: 1983, Page(s):121 - 127
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    Low-power CMOS op amps with high-drive capability and good settling characteristics are described. One circuit, occupying 150 mils2 of active area and consuming 1 mW of power drives a capacitive load of up to 150 pF with greater than +-2.5 V/µs slew rates and less than 3.5 µs settling time to 0.1 percent. A somewhat larger circuit drives low-resistance (e.g., 600 Omega) and hi... View full abstract»

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  • Real-Time Implementation of Time Domain Harmonic Scaling of Speech for Rate Modification and Coding

    Publication Year: 1983, Page(s):10 - 24
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2352 KB)

    Time domain harmonic scaling (TDHS) has been realized in real time on the Bell Laboratories digital signal processing (DSP) integrated circuit. It is an algorithm that can expand or compress the bandwidth and sampling rate of speech by taking advantage of the pitch structure in the speech signal. As such it is useful in a variety of speech applications including speech coding, speech enhancement, ... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com