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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1982

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Displaying Results 1 - 25 of 42
  • [Inside front cover - December 1982]

    Page(s): f2
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    Freely Available from IEEE
  • 1982 Index IEEE Journal of Solid-State Circuits Vol. SC-17

    Page(s): i1 - i17
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    Freely Available from IEEE
  • Table of contents (December 1982)

    Page(s): 965 - 966
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    Freely Available from IEEE
  • Foreword (December 1982)

    Page(s): 967 - 968
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    Freely Available from IEEE
  • MOS operational amplifier design-a tutorial overview

    Page(s): 969 - 982
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    Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aspects are summarized, and examples are given. View full abstract»

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  • A low-noise NMOS operational amplifier

    Page(s): 999 - 1008
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    NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW. View full abstract»

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  • A MOS switched-capacitor instrumentation amplifier

    Page(s): 1008 - 1013
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    Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample. View full abstract»

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  • A family of differential NMOS analog circuits for a PCM codec filter chip

    Page(s): 1014 - 1023
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    A new NMOS PCM codec filter uses low-noise fully differential circuits to achieve supply rejection of 36 dB and idle channel noise of 6 dB/SUB rnc0/. The die size is 24 mm/SUP 2/ and the active standby power is 150 mW/5 mW. View full abstract»

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  • A differential narrow-band switched capacitor filtering technique

    Page(s): 1029 - 1038
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    A new resonator loss cancellation technique is described using NMOS technology. It allows the implementation of high Q switched capacitor band-pass filters using single-stage low-gain amplifiers. The approach exchanges the amplifier high DC-gain requirement by a gain matching between amplifiers of the same resonator. A prototype sixth-order bandpass filter with center frequency of 100 kHz and a 5 kHz bandwidth was built to demonstrate the feasibility of the technique. Unloaded resonator quality factors of the order of 400 were achieved using amplifiers with a DC gain of 50. View full abstract»

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  • A single-chip NMOS analog front-end LSI for modems

    Page(s): 1039 - 1044
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    Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size. View full abstract»

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  • Characterization of individual weights in transversal filters and application to CCDs

    Page(s): 1054 - 1061
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    Time-domain sampling and averaging techniques for direct measurement of individual tap weights of transversal filters are considered. The essential features of the measurement and the corresponding instrumentation requirements are discussed from a general viewpoint; guidelines are determined for the implementation of measurement set-ups by using existing circuits and instruments. An application of the technique to the characterization of split-electrode CCD filters is then considered in detail and criteria for the analysis of experimental data are discussed. It is shown that separate evaluation of different sources of errors in the tap weights is possible. In particular, in the devices experimentally studied, three known error sources were quantitatively analyzed: charge-transfer inefficiency, mask misalignments, and uneven charge repartition. Application of the same techniques is also envisaged for the characterization of other CCD devices such as delay lines and imagers. View full abstract»

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  • A CMOS/CCD 256-stage programmable transversal filter

    Page(s): 1062 - 1069
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    A 256-stage programmable analog-binary correlator fabricated in a combined CMOS buried n-channel CCD technology is reported. The correlator features three-level reference weighting at each stage (+1, -1, 0), low code dependent bias, automatic CCD input bias adjustment, high-speed clock drivers, and low power dissipation. Correlation performance is presented at sampling frequencies from 10 kHz to 25 MHz. View full abstract»

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  • A precision variable-supply CMOS comparator

    Page(s): 1080 - 1087
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    Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V. View full abstract»

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  • A fast latching current comparator for 12-bit A/D applications

    Page(s): 1088 - 1094
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    Describes a novel monolithic high-speed comparator which senses the polarity of the input current rather than voltage. The new approach greatly reduces overall system conversion time for a successive approximation 12-bit A/D converter. The circuit features a single input pin for polarity discrimination, dual complementary outputs, and fast response time of 72 ns to 0.5 LSB overdrive (500 nA). The sum of the total error due to the comparator is 0.2 LSB with respect to the input. The comparator is manufactured on a bipolar, ion-implanted base, 9 /spl mu/m epi, junction-isolated process. View full abstract»

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  • Design considerations for linear optically coupled isolation amplifiers

    Page(s): 1094 - 1101
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    A hybrid optically coupled isolation amplifier is described which optimizes DC performance, bandwidth, physical size, and cost. The design utilizes a blend of monolithic and hybrid technologies to achieve this unique set of characteristics. The development of the linear optical coupler is traced. Optical and electronic circuit techniques are presented that combine, for the first time, precision performance with miniature packaging. Optional connections allow unipolar/bipolar and inverting/noninverting operation with both voltage and current inputs. Typical performance, based upon production runs, includes: 1000 V isolation voltage, 10 nA offset current, 1 pA//spl deg/C offset drift, 0.3 /spl mu/A barrier leakage at 60 Hz, 0.05 percent nonlinearity, and a bandwidth of over 60 kHz. View full abstract»

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  • A programmable instrumentation amplifier for 12-bit resolution systems

    Page(s): 1102 - 1111
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    Describes the design of and experimental results obtained from a monolithic gain-programmable instrumentation amplifier that attains performance compatible with 12-bit or higher resolution data acquisition systems. Nonlinearity is held to a 0.01 percent worst-case level over the -25 to 85/spl deg/C temperature range for gains of 1-1000, independent of process variations. Input and output voltage noise and offset drift are also reduced to low levels. A novel input overvoltage protection scheme is also described. The amplifier is fabricated on a standard-beta junction isolated bipolar process that has in addition process-compatible ion implanted JFETs and silicon-chromium thin-film resistors. View full abstract»

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  • A monolithic 14 bit A/D converter

    Page(s): 1112 - 1117
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    A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped operational amplifier followed by a strobed flip-flop to freeze the output data. In the digital part, current mode logic (CML) is used for speed and low interference generation with respect to the analog circuitry. Digital input and outputs are TTL compatible. A low-noise, high-stability reference source with a temperature dependence of /spl plusmn/0.5 ppm//spl deg/C over -20 to +85/spl deg/C completes the A/D function. The chip is processed in a standard bipolar process using double layer interconnection. The die size is 3.5/spl times/4.4 mm/SUP 2/. View full abstract»

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  • A 14 bit dual-ramp DAC for digital-audio systems

    Page(s): 1118 - 1126
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    A 14 bit digital-to-analog converter system based upon a dual-ramp technique has been fabricated in a standard monolithic bipolar process. The system features a precision sample-and-hold amplifier and postpackage trim for 0.003 percent linearity. The conversion time is 20 /spl mu/s. View full abstract»

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  • A sixteen-bit monolithic bipolar DAC

    Page(s): 1127 - 1132
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    Describes a fully monolithic 16-bit digital-analog converter (DAC) which is fabricated with dielectric isolation and thin film nichrome resistors. The design uses a straightforward extension of techniques successfully used in lower resolution DACs. To achieve the greater accuracy needed for a 16-bit DAC, special layout techniques are used. An auxiliary R-2R ladder is introduced to provide a ground current cancellation scheme. The experimental results show that 16-bit resolution is possible with a typical settling time of 1 /spl mu/s. Improved performance over a temperature range of 0/spl deg/C-75/spl deg/C is observed with units exhibiting one-half an LSB differential and integral linearity of 14-bit resolution. The initial 16-bit accuracy approaches that of expensive hybrid modules, while the accuracy over wide temperature ranges surpasses anything presently reported. View full abstract»

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  • A fully parallel 10-bit A/D converter with video speed

    Page(s): 1133 - 1138
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    Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip. View full abstract»

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  • A new curvature-corrected bandgap reference

    Page(s): 1139 - 1143
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    A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V. View full abstract»

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  • High-voltage subscriber line interface LSIs

    Page(s): 1144 - 1149
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    A high-voltage BORSHT LSI family for an all solid-state subscriber line interface circuit in a digital local switching system has been developed. The family consists of a 320 V dielectrically isolated RTLSI, a 60 V bipolar BSH-LSI, and a CMOS control LSI. Ringing, reverse, and network-test functions were implemented in the RT-LSI chip using a high-voltage current-controlled p-n-p-n-switch integration technology. Battery feed, supervision, and hybrid functions have been integrated into the BSH-LSI chip using a high-precision analog bipolar process technology. The CMOS logic LSI performs a digital interface function with the PCM highway, as well as a control function for the other LSIs. Using this BORSHT LSI family along with a codec, it has become possible to make a low-cost and small-size subscriber line interface circuit for central office use. View full abstract»

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  • A programmable speech circuit suitable for telephone transducers

    Page(s): 1149 - 1157
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    To satisfy the differing requirements of various telecommunication administrations and to accommodate the characteristics of different transducers, a number of electronic speech circuits have been developed. To avoid this proliferation of types, a new programmable speech circuit, based on an improved bipolar process, has been developed. This speech circuit is suitable for many transducer types-dynamic, piezoceramic, and electret microphones-and provides 6 dB of programmable gain in both directions to compensate for line length. View full abstract»

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  • A carrier current transceiver IC for data transmission over the AC power lines

    Page(s): 1158 - 1165
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    A monolithic solution to the problem of sending and receiving data over power lines has been developed. The self-contained bipolar chip handles half-duplex serial data at up to 4K baud by FSK modulating a carrier frequency set at between 50 and 300 kHz. The transmitter section drives the line with a low distortion (0.1 percent) sine wave to minimize potential RFI. The 200 mW output originates from a transient-hardened on-chip transistor, and is in the form of a current that adapts to the widely varying power line impedance. The PLL receiver section has a sensitivity of 1 mV and contains a special impulse noise filter to reduce the effects of power line noise. Data of virtually any coding will pass through the system. View full abstract»

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  • A monolithic wide-band GaAs IC amplifier

    Page(s): 1166 - 1173
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    The design and performance of a general purpose, monolithic, wide-band GaAs IC amplifier is described. This amplifier features a high-voltage gain (26 dB), wide bandwidth (5 MHz to 3.3 GHz), and very low input: VSWR (less than 1.3:1). No matching components are used on-chip, allowing for a small chip size of /SUP 1///SUB 4/ mm/SUP 2/. The input stage consists of a 248 /spl mu/m MESFET in a common-gate configuration with a noise figure under 10 dB (f=1 GHz) with a 50 /spl Omega/ source resistance. Noise figure limitations of both common-source and common-gate MESFET stages are discussed in detail. The amplifier uses 1 /spl mu/m gate length MESFETs, GaAs Schottky diodes for level shifting, thin-film silicon nitride capacitors for AC coupling, and GaAs implanted resistors. The high gain and wide bandwidth make this amplifier useful for many signal processing and instrument/measurement applications. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan