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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Dec. 1982

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Displaying Results 1 - 25 of 42
  • [Inside front cover - December 1982]

    Publication Year: 1982 , Page(s): f2
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    Freely Available from IEEE
  • 1982 Index IEEE Journal of Solid-State Circuits Vol. SC-17

    Publication Year: 1982 , Page(s): i1 - i17
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    Freely Available from IEEE
  • Table of contents (December 1982)

    Publication Year: 1982 , Page(s): 965 - 966
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    Freely Available from IEEE
  • Foreword (December 1982)

    Publication Year: 1982 , Page(s): 967 - 968
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    Freely Available from IEEE
  • MOS operational amplifier design-a tutorial overview

    Publication Year: 1982 , Page(s): 969 - 982
    Cited by:  Papers (203)  |  Patents (51)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1520 KB)  

    Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar... View full abstract»

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  • A low-noise NMOS operational amplifier

    Publication Year: 1982 , Page(s): 999 - 1008
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (752 KB)  

    NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW. View full abstract»

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  • A MOS switched-capacitor instrumentation amplifier

    Publication Year: 1982 , Page(s): 1008 - 1013
    Cited by:  Papers (53)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (933 KB)  

    Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential co... View full abstract»

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  • A family of differential NMOS analog circuits for a PCM codec filter chip

    Publication Year: 1982 , Page(s): 1014 - 1023
    Cited by:  Papers (85)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1349 KB)  

    A new NMOS PCM codec filter uses low-noise fully differential circuits to achieve supply rejection of 36 dB and idle channel noise of 6 dB/SUB rnc0/. The die size is 24 mm/SUP 2/ and the active standby power is 150 mW/5 mW. View full abstract»

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  • A differential narrow-band switched capacitor filtering technique

    Publication Year: 1982 , Page(s): 1029 - 1038
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1068 KB)  

    A new resonator loss cancellation technique is described using NMOS technology. It allows the implementation of high Q switched capacitor band-pass filters using single-stage low-gain amplifiers. The approach exchanges the amplifier high DC-gain requirement by a gain matching between amplifiers of the same resonator. A prototype sixth-order bandpass filter with center frequency of 100 kHz and a 5 ... View full abstract»

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  • A single-chip NMOS analog front-end LSI for modems

    Publication Year: 1982 , Page(s): 1039 - 1044
    Cited by:  Papers (6)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (862 KB)  

    Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero cro... View full abstract»

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  • Characterization of individual weights in transversal filters and application to CCDs

    Publication Year: 1982 , Page(s): 1054 - 1061
    Cited by:  Papers (2)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (965 KB)  

    Time-domain sampling and averaging techniques for direct measurement of individual tap weights of transversal filters are considered. The essential features of the measurement and the corresponding instrumentation requirements are discussed from a general viewpoint; guidelines are determined for the implementation of measurement set-ups by using existing circuits and instruments. An application of... View full abstract»

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  • A CMOS/CCD 256-stage programmable transversal filter

    Publication Year: 1982 , Page(s): 1062 - 1069
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1424 KB)  

    A 256-stage programmable analog-binary correlator fabricated in a combined CMOS buried n-channel CCD technology is reported. The correlator features three-level reference weighting at each stage (+1, -1, 0), low code dependent bias, automatic CCD input bias adjustment, high-speed clock drivers, and low power dissipation. Correlation performance is presented at sampling frequencies from 10 kHz to 2... View full abstract»

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  • A precision variable-supply CMOS comparator

    Publication Year: 1982 , Page(s): 1080 - 1087
    Cited by:  Papers (67)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1181 KB)  

    Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings... View full abstract»

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  • A fast latching current comparator for 12-bit A/D applications

    Publication Year: 1982 , Page(s): 1088 - 1094
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1317 KB)  

    Describes a novel monolithic high-speed comparator which senses the polarity of the input current rather than voltage. The new approach greatly reduces overall system conversion time for a successive approximation 12-bit A/D converter. The circuit features a single input pin for polarity discrimination, dual complementary outputs, and fast response time of 72 ns to 0.5 LSB overdrive (500 nA). The ... View full abstract»

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  • Design considerations for linear optically coupled isolation amplifiers

    Publication Year: 1982 , Page(s): 1094 - 1101
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1298 KB)  

    A hybrid optically coupled isolation amplifier is described which optimizes DC performance, bandwidth, physical size, and cost. The design utilizes a blend of monolithic and hybrid technologies to achieve this unique set of characteristics. The development of the linear optical coupler is traced. Optical and electronic circuit techniques are presented that combine, for the first time, precision pe... View full abstract»

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  • A programmable instrumentation amplifier for 12-bit resolution systems

    Publication Year: 1982 , Page(s): 1102 - 1111
    Cited by:  Papers (6)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1630 KB)  

    Describes the design of and experimental results obtained from a monolithic gain-programmable instrumentation amplifier that attains performance compatible with 12-bit or higher resolution data acquisition systems. Nonlinearity is held to a 0.01 percent worst-case level over the -25 to 85/spl deg/C temperature range for gains of 1-1000, independent of process variations. Input and output voltage n... View full abstract»

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  • A monolithic 14 bit A/D converter

    Publication Year: 1982 , Page(s): 1112 - 1117
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (726 KB)  

    A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped ... View full abstract»

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  • A 14 bit dual-ramp DAC for digital-audio systems

    Publication Year: 1982 , Page(s): 1118 - 1126
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1484 KB)  

    A 14 bit digital-to-analog converter system based upon a dual-ramp technique has been fabricated in a standard monolithic bipolar process. The system features a precision sample-and-hold amplifier and postpackage trim for 0.003 percent linearity. The conversion time is 20 /spl mu/s. View full abstract»

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  • A sixteen-bit monolithic bipolar DAC

    Publication Year: 1982 , Page(s): 1127 - 1132
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (897 KB)  

    Describes a fully monolithic 16-bit digital-analog converter (DAC) which is fabricated with dielectric isolation and thin film nichrome resistors. The design uses a straightforward extension of techniques successfully used in lower resolution DACs. To achieve the greater accuracy needed for a 16-bit DAC, special layout techniques are used. An auxiliary R-2R ladder is introduced to provide a ground... View full abstract»

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  • A fully parallel 10-bit A/D converter with video speed

    Publication Year: 1982 , Page(s): 1133 - 1138
    Cited by:  Papers (26)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (923 KB)  

    Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a pa... View full abstract»

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  • A new curvature-corrected bandgap reference

    Publication Year: 1982 , Page(s): 1139 - 1143
    Cited by:  Papers (25)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (606 KB)  

    A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V. View full abstract»

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  • High-voltage subscriber line interface LSIs

    Publication Year: 1982 , Page(s): 1144 - 1149
    Cited by:  Papers (5)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1251 KB)  

    A high-voltage BORSHT LSI family for an all solid-state subscriber line interface circuit in a digital local switching system has been developed. The family consists of a 320 V dielectrically isolated RTLSI, a 60 V bipolar BSH-LSI, and a CMOS control LSI. Ringing, reverse, and network-test functions were implemented in the RT-LSI chip using a high-voltage current-controlled p-n-p-n-switch integrat... View full abstract»

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  • A programmable speech circuit suitable for telephone transducers

    Publication Year: 1982 , Page(s): 1149 - 1157
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (881 KB)  

    To satisfy the differing requirements of various telecommunication administrations and to accommodate the characteristics of different transducers, a number of electronic speech circuits have been developed. To avoid this proliferation of types, a new programmable speech circuit, based on an improved bipolar process, has been developed. This speech circuit is suitable for many transducer types-dyn... View full abstract»

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  • A carrier current transceiver IC for data transmission over the AC power lines

    Publication Year: 1982 , Page(s): 1158 - 1165
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (957 KB)  

    A monolithic solution to the problem of sending and receiving data over power lines has been developed. The self-contained bipolar chip handles half-duplex serial data at up to 4K baud by FSK modulating a carrier frequency set at between 50 and 300 kHz. The transmitter section drives the line with a low distortion (0.1 percent) sine wave to minimize potential RFI. The 200 mW output originates from... View full abstract»

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  • A monolithic wide-band GaAs IC amplifier

    Publication Year: 1982 , Page(s): 1166 - 1173
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1052 KB)  

    The design and performance of a general purpose, monolithic, wide-band GaAs IC amplifier is described. This amplifier features a high-voltage gain (26 dB), wide bandwidth (5 MHz to 3.3 GHz), and very low input: VSWR (less than 1.3:1). No matching components are used on-chip, allowing for a small chip size of /SUP 1///SUB 4/ mm/SUP 2/. The input stage consists of a 248 /spl mu/m MESFET in a common-... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan