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Solid-State Circuits, IEEE Journal of

Issue 3 • Date June 1982

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Displaying Results 1 - 25 of 37
  • [Inside front cover - June 1982]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1982)

    Page(s): 437 - 438
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    Freely Available from IEEE
  • Editor's Note (June 1982)

    Page(s): 439
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    Freely Available from IEEE
  • Foreword: Special Issue on the Seventh European Solid-State Circuits Conference

    Page(s): 440 - 441
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    Freely Available from IEEE
  • A highly automated semi-custom approach for VLSI

    Page(s): 465 - 472
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    The structured approach is aimed at optimizing the chip physical design while keeping design resources and time at a reasonable level. The logic is partitioned into data flow logic and control logic; a specialized physical structure has been defined to match the data flow logic structure and the gate array has been chosen for control logic implementation, both physical structures being customizable. A general purpose library and a set of design automation programs have been developed to allow fast physical design of the functional partitions according to the applications. A bipolar 16-bit slice microprocessor has been designed with this approach and built; compared to the widely used gate array chip implementation, it shows an improvement of 2 in gate density and 1.5 in power dissipation. The physical design of this 2000 gates chip took only two months. View full abstract»

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  • A study on bipolar VLSI gate-arrays assuming four layers of metal

    Page(s): 472 - 480
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    Describes a design study on a bipolar gate-array or masterslice chip with almost 10000 circuits. It assumes 2.5 /spl mu/m groundrules and four layers of metal, i.e. three layers of metal for global wiring and one layer for power and I/O redistribution. It is proven by using actual logic from the IBM 4331 system, that an additional wiring layer increases the circuit density on a masterslice chip by more than a factor of 2. The paper is divided into three sections. Section 1 describes the chip design, the detailed arrangement of internal and external cells with the associated wiring channels and some general aspects of a masterslice design. Section II explains the placement and wiring tools and gives detailed results of a wiring study, comparing a logic design with 2 wiring layers with the same logic implemented with 3 wiring layers (4 layers total). Section III covers the off-chip communication with its associated problems like noise generation by simultaneous driver switching, three-state driver, and embedded RAM macro testing. View full abstract»

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  • An integrated telephone speech circuit including a line fed loudspeaker amplifier

    Page(s): 494 - 498
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    A new electronic speech circuit is described which replaces carbon microphone, hybrid transducer, sidetone network and click suppressor of the conventional telephone set. A low cost dynamic transducer is used instead of microphone and earphone. A low cost loudspeaker may also be used. The circuit is fed from DC line current by a special current source and contains a loudspeaker amplifier, other necessary amplifiers, a circuit for compensating line attenuation dependent on DC line current, and a stabilized DC voltage source, from which almost the whole DC line current may be drawn for other circuits too. Tone quality has been considerably improved in comparison with conventional telephone sets. View full abstract»

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  • Adaptive biasing CMOS amplifiers

    Page(s): 522 - 528
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    Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifiers presented earlier. The second amplifier can be used as a micropower buffer. Nearly the whole supply current is used to charge the load capacitor so that this amplifier has a high efficiency. View full abstract»

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  • A high-speed comparator design technique

    Page(s): 529 - 532
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    Fast comparators are an essential feature of many new circuit applications, including optical fiber links, nucleonics, and data converters. The author describes a design approach based on large signal linear circuitry which is capable of providing high gain (>55 dB), low propagation delay (1.5 ns) comparators, either singly or for use in arrays. Outstanding features of the circuit are high gain at high frequency and the minimal variation of delay with overdrive conditions. A junction isolated bipolar process is used which has 3 /spl mu/m minimum feature size and 5 GHz transistor f/SUB T/'s. View full abstract»

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  • A 32-bit execution unit in an advanced NMOS technology

    Page(s): 533 - 538
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    The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations and has an on-chip control ROM for instruction decoding. It operates with a single 5-V supply voltage. Measurements resulted in a typical power dissipation of 750 mW and a maximum operation frequency of 6.5 MHz. At this frequency a 32/spl times/32 bit multiplication is performed in less than 5.5 /spl mu/s. View full abstract»

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  • A novel associative approach for fault-tolerant MOS RAMs

    Page(s): 539 - 546
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    A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well. View full abstract»

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  • A 4-valued ECL encoder and decoder circuit

    Page(s): 547 - 552
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    The authors present the prototype of a 4-valued ECL encoder and decoder circuit that has been designed as a test chip for the realization of 4-valued cells to be used in interconnection networks. The hardware implementation of such a network in a SIMD or a MIMD computer architecture leads to a significant reduction of the number of wires. Static and dynamic characteristics are presented together with results on the propagation of 4-valued signals. Noise margins are compared for 2-valued and 4-valued versions. View full abstract»

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  • A single chip regenerator for transmission systems operating in the range 2-320 Mbits/s

    Page(s): 553 - 558
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    Circuit and operational details of a single chip regenerator, developed by BTRL, are presented. The device is capable of operation over the entire span of currently agreed CCITT hierarchical transmission levels from 2 Mbit/s to 140 Mbits/s. Extension to 280 Mbits/s (320 MBd when coded by 7B8B for optical system applications) is also demonstrated to be possible. View full abstract»

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  • A programmable gate array based integrated circuit for high bit rate telecommunications transmission system applications

    Page(s): 586 - 588
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    A prototype device is described which uses an ECL gate array to meet several of the terminal circuit requirements of high bit rate telecommunications transmission systems. A `Westcott' data test set and two kinds of scrambler/descramblers have been produced as a single externally programmable integrated circuit. The structure and facilities are discussed together with the performance of a batch of 50 devices which indicate a capability of 280 Mbit/s and above. View full abstract»

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  • A novel MOS compatible light intensity-to-frequency converter suited for monolithic integration

    Page(s): 588 - 591
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    A novel circuit for light intensity-to-frequency conversion (LFC) suited for monolithic integration in MOS technologies is presented. The function is based on an R~S~ flip-flop whose toggle frequency is controlled by the discharge of a capacitance at the inputs of the R~S~ FF. For homogeneous illumination, the output frequency is proportional to the incident light level. For an implemented device, a dynamic range of more than six decades (approximately 0.2 lux up to >2/spl times/10/SUP 5/ lux) and a range of linearity of five decades were found. View full abstract»

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  • An integrated amplifier for an active car-radio antenna

    Page(s): 591 - 593
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    An integrated amplifier for a very short active car-radio antenna (l=30 cm) for the 100 kHz-6 MHz range is presented. A JFET input stage, together with a low input impedance realized by overall feedback, yields excellent noise and intermodulation performance, and allows easy input protection. Field strengths as high as 8 V/cm can be handled without significant cross modulation. View full abstract»

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  • A two-device bistable memory circuit without feedback loop

    Page(s): 593 - 596
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    A gate-controlled diode is operated as a bistable device in a two-device configuration without feedback loop. The analysis of bistability and its experimental verification are presented, and a potential use of the bistable circuit in dense and low-powered pseudostatic RAM cells is discussed. View full abstract»

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  • A low-power easy-to-calibrate temperature transducer

    Page(s): 609 - 613
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    This paper describes a modified IC temperature transducer with an intrinsic reference whose main features are: easy calibration (in a single step), high sensitivity over a wide temperature range (-4.6 mV//spl deg/C; -50/spl deg/C to +125/spl deg/C), low output impedance (40 /spl Omega/), and low-power dissipation (200 /spl mu/W). The device in which diffused resistors are applied has been fabricated in a conventional IC process. Its application in thermocouple cold-junction compensation is discussed. View full abstract»

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  • [Back inside cover - June 1982]

    Page(s): b1
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    Freely Available from IEEE
  • CAD model for threshold and subthreshold conduction in MOSFETs

    Page(s): 454 - 458
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    The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion. The proposed model shows better agreement to experimental results than previous models in the subthreshold and threshold regions, and is well suited for use in circuit simulation programs; the authors have implemented it in MSINC and SPICE programs, and simulation results are compared to experimental data for a micropower amplifier. View full abstract»

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  • MAIL-a new Josephson logic family

    Page(s): 562 - 568
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    A novel family of Josephson logic circuits called magnetically coupled asymmetric interferometer logic (MAIL) has been designed. The basic MAIL device is an asymmetric two-Josephson-junction interferometer. Computer simulations of OR/AND MAIL circuits using 2.5 μm Pb/Pb technology device models indicate an unloaded logic-gate delay of approximately 25 ps and a power dissipation of 5 μW/gate. Thus, the power-delay product is only 125 Atto J. Different MAIL logic gates have been tested experimentally, and preliminary results are presented. View full abstract»

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  • GaAs MESFET ICs for gigabit logic applications

    Page(s): 569 - 584
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    This paper gives an overview of the basic concepts used in the design and fabrication of gallium arsenide MESFET integrated circuits intended for gigabit logic applications. The present status of speed-power performances, packing densities, and integration levels is presented on the basis of some MSI and LSI MESFET IC realizations made possible by the principal GaAs logic approaches to date. Finally, the potential field of application and future trends of GaAs IC technology are assessed. View full abstract»

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  • Real-time programmable low power SC bandpass filter

    Page(s): 499 - 506
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    A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 μW at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology. View full abstract»

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  • Charge domain recursive filters

    Page(s): 597 - 605
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    A new charge-transfer device architecture has been developed for implementing recursive filters in the minority charge domain. A three pole filter using this architecture has been designed and fabricated. The measured filter characteristics are in close agreement with theoretical predictions to approximately 0.2 percent. The charge domain filter appears to retain the intrinsic CCD shift register advantages (e.g. high-speed, small output capacitance, wide linear dynamic range), while overcoming many of the disadvantages of the present CCD transversal filter architecture. View full abstract»

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  • On the integration of an internal human conditioning system

    Page(s): 513 - 521
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    Medical equipment is reviewed for its relative importance in sales and for its suitability to be integrated. It is shown how most implantable circuit configurations can be derived from an internal human conditioning system (IHCS), which carries out all elementary functions of measurement and stimulation in the human body. The potential integration of such an IHCS is discussed. For the sake of illustration a number of devices and circuits are presented, such as a low-power VCO, a micropower op amp, a biotelemetry chip, and an ear stimulator decoder chip. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan