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IEEE Journal of Solid-State Circuits

Issue 3 • June 1982

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Displaying Results 1 - 25 of 37
  • [Inside front cover - June 1982]

    Publication Year: 1982, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1982)

    Publication Year: 1982, Page(s):437 - 438
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    Freely Available from IEEE
  • Editor's Note (June 1982)

    Publication Year: 1982, Page(s): 439
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    Freely Available from IEEE
  • Foreword: Special Issue on the Seventh European Solid-State Circuits Conference

    Publication Year: 1982, Page(s):440 - 441
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    Freely Available from IEEE
  • A highly automated semi-custom approach for VLSI

    Publication Year: 1982, Page(s):465 - 472
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1315 KB)

    The structured approach is aimed at optimizing the chip physical design while keeping design resources and time at a reasonable level. The logic is partitioned into data flow logic and control logic; a specialized physical structure has been defined to match the data flow logic structure and the gate array has been chosen for control logic implementation, both physical structures being customizabl... View full abstract»

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  • A study on bipolar VLSI gate-arrays assuming four layers of metal

    Publication Year: 1982, Page(s):472 - 480
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2029 KB)

    Describes a design study on a bipolar gate-array or masterslice chip with almost 10000 circuits. It assumes 2.5 /spl mu/m groundrules and four layers of metal, i.e. three layers of metal for global wiring and one layer for power and I/O redistribution. It is proven by using actual logic from the IBM 4331 system, that an additional wiring layer increases the circuit density on a masterslice chip by... View full abstract»

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  • An integrated telephone speech circuit including a line fed loudspeaker amplifier

    Publication Year: 1982, Page(s):494 - 498
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (789 KB)

    A new electronic speech circuit is described which replaces carbon microphone, hybrid transducer, sidetone network and click suppressor of the conventional telephone set. A low cost dynamic transducer is used instead of microphone and earphone. A low cost loudspeaker may also be used. The circuit is fed from DC line current by a special current source and contains a loudspeaker amplifier, other ne... View full abstract»

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  • Adaptive biasing CMOS amplifiers

    Publication Year: 1982, Page(s):522 - 528
    Cited by:  Papers (170)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1055 KB)

    Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifie... View full abstract»

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  • A high-speed comparator design technique

    Publication Year: 1982, Page(s):529 - 532
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Fast comparators are an essential feature of many new circuit applications, including optical fiber links, nucleonics, and data converters. The author describes a design approach based on large signal linear circuitry which is capable of providing high gain (>55 dB), low propagation delay (1.5 ns) comparators, either singly or for use in arrays. Outstanding features of the circuit are high gain... View full abstract»

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  • A 32-bit execution unit in an advanced NMOS technology

    Publication Year: 1982, Page(s):533 - 538
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (983 KB)

    The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations ... View full abstract»

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  • A novel associative approach for fault-tolerant MOS RAMs

    Publication Year: 1982, Page(s):539 - 546
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1229 KB)

    A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concep... View full abstract»

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  • A 4-valued ECL encoder and decoder circuit

    Publication Year: 1982, Page(s):547 - 552
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (786 KB)

    The authors present the prototype of a 4-valued ECL encoder and decoder circuit that has been designed as a test chip for the realization of 4-valued cells to be used in interconnection networks. The hardware implementation of such a network in a SIMD or a MIMD computer architecture leads to a significant reduction of the number of wires. Static and dynamic characteristics are presented together w... View full abstract»

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  • A single chip regenerator for transmission systems operating in the range 2-320 Mbits/s

    Publication Year: 1982, Page(s):553 - 558
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (975 KB)

    Circuit and operational details of a single chip regenerator, developed by BTRL, are presented. The device is capable of operation over the entire span of currently agreed CCITT hierarchical transmission levels from 2 Mbit/s to 140 Mbits/s. Extension to 280 Mbits/s (320 MBd when coded by 7B8B for optical system applications) is also demonstrated to be possible. View full abstract»

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  • A programmable gate array based integrated circuit for high bit rate telecommunications transmission system applications

    Publication Year: 1982, Page(s):586 - 588
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (566 KB)

    A prototype device is described which uses an ECL gate array to meet several of the terminal circuit requirements of high bit rate telecommunications transmission systems. A `Westcott' data test set and two kinds of scrambler/descramblers have been produced as a single externally programmable integrated circuit. The structure and facilities are discussed together with the performance of a batch of... View full abstract»

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  • A novel MOS compatible light intensity-to-frequency converter suited for monolithic integration

    Publication Year: 1982, Page(s):588 - 591
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (801 KB)

    A novel circuit for light intensity-to-frequency conversion (LFC) suited for monolithic integration in MOS technologies is presented. The function is based on an R~S~ flip-flop whose toggle frequency is controlled by the discharge of a capacitance at the inputs of the R~S~ FF. For homogeneous illumination, the output frequency is proportional to the incident light level. For an implemented device,... View full abstract»

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  • An integrated amplifier for an active car-radio antenna

    Publication Year: 1982, Page(s):591 - 593
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (559 KB)

    An integrated amplifier for a very short active car-radio antenna (l=30 cm) for the 100 kHz-6 MHz range is presented. A JFET input stage, together with a low input impedance realized by overall feedback, yields excellent noise and intermodulation performance, and allows easy input protection. Field strengths as high as 8 V/cm can be handled without significant cross modulation. View full abstract»

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  • A two-device bistable memory circuit without feedback loop

    Publication Year: 1982, Page(s):593 - 596
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (639 KB)

    A gate-controlled diode is operated as a bistable device in a two-device configuration without feedback loop. The analysis of bistability and its experimental verification are presented, and a potential use of the bistable circuit in dense and low-powered pseudostatic RAM cells is discussed. View full abstract»

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  • A low-power easy-to-calibrate temperature transducer

    Publication Year: 1982, Page(s):609 - 613
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (733 KB)

    This paper describes a modified IC temperature transducer with an intrinsic reference whose main features are: easy calibration (in a single step), high sensitivity over a wide temperature range (-4.6 mV//spl deg/C; -50/spl deg/C to +125/spl deg/C), low output impedance (40 /spl Omega/), and low-power dissipation (200 /spl mu/W). The device in which diffused resistors are applied has been fabricat... View full abstract»

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  • [Back inside cover - June 1982]

    Publication Year: 1982, Page(s): b1
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    Freely Available from IEEE
  • MAIL-a new Josephson logic family

    Publication Year: 1982, Page(s):562 - 568
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    A novel family of Josephson logic circuits called magnetically coupled asymmetric interferometer logic (MAIL) has been designed. The basic MAIL device is an asymmetric two-Josephson-junction interferometer. Computer simulations of OR/AND MAIL circuits using 2.5 μm Pb/Pb technology device models indicate an unloaded logic-gate delay of approximately 25 ps and a power dissipation of 5 μW/gate.... View full abstract»

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  • Charge domain recursive filters

    Publication Year: 1982, Page(s):597 - 605
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1632 KB)

    A new charge-transfer device architecture has been developed for implementing recursive filters in the minority charge domain. A three pole filter using this architecture has been designed and fabricated. The measured filter characteristics are in close agreement with theoretical predictions to approximately 0.2 percent. The charge domain filter appears to retain the intrinsic CCD shift register a... View full abstract»

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  • Complex integrated circuit design strategy

    Publication Year: 1982, Page(s):459 - 464
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    Presents a design strategy for VLSI circuits based on the use of a floor plan as an evaluation and management guide for the design of a future circuit. This approach is widely used in the microelectronic industry and allows global optimizations, which are the key to both high density and design reliability, by improving the assembly and the direct wiring of the blocks. The efficiency of such an ap... View full abstract»

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  • PLA versus bit slice: comparison for a 32 bit ALU

    Publication Year: 1982, Page(s):584 - 586
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    The PLA technique and the slice technique have been chosen to build a 32 bit wide ALU. Both techniques have a high degree of regularity and are used to soften the design time of complex logic circuits. In a given technology, the PLA is approximately twice as fast as the bit-slice solution (22-35 ns), but also needs more area (4.2-1 mm/SUP 2/). View full abstract»

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  • CCD sampling of high-frequency broad-band signals

    Publication Year: 1982, Page(s):619 - 626
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1448 KB)

    Several CCD signal sampling methods are discussed and a CCD input technique with excellent high-speed sampler characteristics is described. The method, a version of the diode-cutoff technique, is being used in a 200 MHz/8 bit transient digitizer system currently under development. DC based signal bandwidth (3 dB) of 600 to 800 MHz has been achieved along with random aperture uncertainty dispersion... View full abstract»

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  • Experimental autofocus system for lens shutter cameras

    Publication Year: 1982, Page(s):558 - 562
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    Research results on a mainly digitally working autofocus system using an optical module without moving parts are presented. The chip was fabricated in a well-established NMOS technology. It contains two linear arrays of 52 photodiodes each and parts of the signal processing necessary to evaluate the appropriate distance zone. Fifteen zones can be resolved between infinity and 1 m. Minimum scene br... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com