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IEEE Journal of Solid-State Circuits

Issue 5 • Oct. 1981

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Displaying Results 1 - 25 of 34
  • [Inside front cover - October 1981]

    Publication Year: 1981, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (October 1981)

    Publication Year: 1981, Page(s): 421
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    Freely Available from IEEE
  • Foreword [to the Special Issue]

    Publication Year: 1981, Page(s):422 - 423
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    Freely Available from IEEE
  • A 3-ns 1-kbit RAM using super self-aligned process technology

    Publication Year: 1981, Page(s):424 - 429
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1211 KB)

    A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM. View full abstract»

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  • High-speed split-emitter I/sup 2/L/MTL memory cell

    Publication Year: 1981, Page(s):429 - 434
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (785 KB)

    Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental i... View full abstract»

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  • A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM

    Publication Year: 1981, Page(s):435 - 443
    Cited by:  Papers (33)  |  Patents (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1688 KB)

    A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell con... View full abstract»

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  • A 30 ns 16Kx1 fully static RAM

    Publication Year: 1981, Page(s):444 - 448
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1295 KB)

    A fully static 16K/spl times/1 random access memory (SRAM) with significantly improved speed is discussed. Design innovations using conservative 2.5 /spl mu/m transistors and state-of-the-art double level poly (DLP) scaled NMOS technology were utilized to accomplish 30 ns address and chip select access times with an active power of 550 mW and standby power of 75 mW. A cost effective DLP process wa... View full abstract»

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  • A high-speed Hi-CMOSII 4K static RAM

    Publication Year: 1981, Page(s):449 - 453
    Cited by:  Papers (11)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1149 KB)

    Using advanced high-performance CMOS (Hi-CMOSII) technology and a high-speed circuit technique, a fully static 4096-word by one-bit RAM with typical address access time of 18 ns and power dissipation of 150 mW has been designed. The power-access-time product realized by the design is almost an order of magnitude better than existing NMOS 4K static RAMs. Moreover, to produce low-cost high-density s... View full abstract»

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  • An 18 ns CMOS/SOS 4K static RAM

    Publication Year: 1981, Page(s):460 - 465
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1106 KB)

    A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of th... View full abstract»

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  • A DOL CMOS static memory cell

    Publication Year: 1981, Page(s):466 - 471
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB)

    A new CMOS static memory cell, called the double-lambda diode (DOL), is described. It offers the speed and the power dissipation advantages of conventional CMOS static memory cells at half the area. The cell uses complementary depletion MOS devices. The processing technology is based on a twin-tub CMOS process. Using 2.5 /spl mu/m design rules the cell area is 500 /spl mu/m/SUP 2/. In addition, a ... View full abstract»

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  • A 4Kx8 dynamic RAM with self-refresh

    Publication Year: 1981, Page(s):479 - 487
    Cited by:  Papers (5)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1126 KB)

    A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refr... View full abstract»

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  • A 16 DIP, 64 kbit, static MOS-RAM

    Publication Year: 1981, Page(s):488 - 491
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (862 KB)

    A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which ... View full abstract»

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  • A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

    Publication Year: 1981, Page(s):499 - 505
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1087 KB)

    Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and comparable performance is obtained using a low-resistance polycide word line. Hi-C implants in the storag... View full abstract»

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  • A 32-bit VLSI CPU chip

    Publication Year: 1981, Page(s):537 - 542
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1058 KB)

    A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating... View full abstract»

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  • An nMOS VLSI process for fabrication of a 32-bit CPU chip

    Publication Year: 1981, Page(s):542 - 547
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1335 KB)

    An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology utilizes 1.5-/spl mu/m lines and 1.0-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization. The device and interconnect structure for this 8-mask process is outlined as a se... View full abstract»

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  • A 32-bit microprocessor with virtual memory support

    Publication Year: 1981, Page(s):548 - 557
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1097 KB)

    A 32-bit microprocessor which supports demand paged virtual memory is described. The processor is implemented on a 290 mil/SUP 2/ chip containing approximately 60K transistors with a 3.5 /spl mu/m gate NMOS technology. The effect of software architecture and performance requirements on chip design is discussed, with particular emphasis on the special problems of supporting virtual memory. The meth... View full abstract»

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  • A bipolar 2500-gate subnanosecond masterslice LSI

    Publication Year: 1981, Page(s):558 - 562
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (950 KB)

    A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power ... View full abstract»

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  • An electrically alterable PLA for fast turnaround-time VLSI development hardware

    Publication Year: 1981, Page(s):570 - 577
    Cited by:  Papers (2)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (950 KB)

    An electrically alterable PLA (EAPLA) has been designed in double polysilicon FET technology to serve as fast turnaround-time development hardware for custom VLSI designs. Included are descriptions of the cell design, the unique circuitry that is used, the chip architecture and a description of the PLA-based design system incorporating the EAPLA. The PLA architecture consists of two arrays cascade... View full abstract»

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  • A 45 ns fully static 16K MOS ROM

    Publication Year: 1981, Page(s):592 - 594
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    Describes a fully static high speed 16 384 bit read only memory (ROM), designed and fabricated by using scaled MOS processing and innovative circuit techniques. Specially designed decoder structures and sense amplifiers enable address accessing in less than 45 ns typically. Extensive use of small signal amplification and 0 volt threshold devices reduce active power to a mere 70 mA, and when the po... View full abstract»

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  • A 20 ns, low power, NMOS 1Kx4 static RAM

    Publication Year: 1981, Page(s):594 - 597
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (795 KB)

    Using scaled NMOS processing and novel circuit design techniques to enhance the speed-power product, a high-speed, low power, fully static 1024-word/spl times/4-bit random access memory has been developed. Applications related requirements such as fast chip select access time and /spl times/4 organization for cache and microcode store memories are central to the device definition. Highly producibl... View full abstract»

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  • Analytic approximations for propagation delays in current-mode switching circuits including collector-base capacitances

    Publication Year: 1981, Page(s):597 - 599
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (343 KB)

    Explicit analytic approximations are given for propagation delays in current-mode switching circuits, including the effects of collector-base capacitances. Accuracies of the approximations, evaluated by comparison with results of numerical computer-aided analysis, are better than /spl plusmn/30 percent. View full abstract»

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  • C/sup 2/MOS 8-bit microprocessor

    Publication Year: 1981, Page(s):599 - 601
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A C/SUP 2/MOS (clocked CMOS) microprocessor is described which is compatible with the standard n-channel 8-bit microprocessor 8080A in both timing and instruction set. It also contains on on-chip clock generator of the 8224 type. Power consumption is about 55 mW, or 1/20 that of the standard 8080A, and the maximum operating clock frequency is about 3 MHz with a 5 V power supply. 6750 MOSFETs are i... View full abstract»

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  • Correction to "A Coplanar CMOS Power Switch"

    Publication Year: 1981, Page(s): 601
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (485 KB)

    Summay form only given, as follows. The photographs accompanying the biographies of E. Habekotte and W. Renker on pages 225 and 226 of the above paper (ibid., vol. SC-16,pp. 212-226, June 1981) were inadvertently interchanged. Also, in Table II on page 223 the Ωcm should instead be Ωcm. View full abstract»

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  • [Back inside cover - October 1981]

    Publication Year: 1981, Page(s): b1
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    Freely Available from IEEE
  • HMOS-CMOS-a low-power high-performance technology

    Publication Year: 1981, Page(s):454 - 459
    Cited by:  Papers (23)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-μm channel length and 400-Å gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single po... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
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jssc.craninckx@gmail.com