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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Aug. 1981

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Displaying Results 1 - 25 of 32
  • [Front cover - August 1981]

    Page(s): f1 - b2
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    Freely Available from IEEE
  • [Inside front cover - August 1981]

    Page(s): f2
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    Freely Available from IEEE
  • Introduction [to the Special Issue]

    Page(s): 245 - 246
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    This is the second special issue on telecommunication circuits to be published in the IEEE Journal of Solid-State Circuits. Since the first was published in February 1979, there have been many advances in ICs for both switching and transmission systems. This issue starts with two overview papers and then presents five groups of papers describing integrated circuits for subscriber-line interfacing and switching, voice coding and decoding, frequency-division multiplexing (FDM), digital network data processing, and signal processing. View full abstract»

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  • A high-voltage IC for a transformerless trunk and subscriber line interface

    Page(s): 261 - 266
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    A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration in transformerless line circuits. The new configuration uses the high-voltage IC plus some low voltage control circuitry to provide limited current battery-feed, loop-closure detection, reverse-battery signaling, two-wire to four-wire conversion, lightning protection, power-down capability, and longitudinal performance which is independent of the battery-feed current magnitude. View full abstract»

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  • A monolithic subscriber line interface circuit [in bipolar technology]

    Page(s): 266 - 270
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    A monolithic SLIC fabricated with high-voltage dielectric isolation (DI) technology has been proven to have excellent performance and requires a minimum of external circuitry. The SLIC provides battery feed, overvoltage protection (with some external devices), ringing control, supervision, and hybrid functions. View full abstract»

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  • A monolithic telephone subscriber loop interface circuit

    Page(s): 270 - 278
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    An integrated circuit that interfaces a subscriber loop with the digital telephone exchange has been produced with conventional high-voltage IC technology. The monolithic SLIC controls DC loop current, converts signal transmission from two-wire to four-wire, and suppresses longitudinal induction. Bias control circuitry automatically reduces standby power when subscriber equipment is detected on-hook. High-voltage circuit techniques maintain performance when the supply voltage exceeds the n-p-n transistor BV/SUB CE0/, and circuit partitioning with two discrete transistors yields manageable junction temperature and an economical 102/spl times/112 mil die size. View full abstract»

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  • A floating, low-power subscriber line interface circuit [bipolar IC technology]

    Page(s): 279 - 285
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    A subscriber line interface circuit is described which is smaller than and dissipates substantially less heat than conventional circuits which perform similar functions. Worst case heat dissipation in the circuit is only 0.65 W as compared to conventional arrangements which dissipate up to 4 W. The battery feed function is accomplished by a small 1.5 W DC-to-DC converter which also includes circuitry for detecting loop supervisory functions. The floating nature of the output circuitry renders it immune to power line induction and common mode power crosses. Primary protection from lightning and other induced surges utilizes conventional carbon block type protectors. Secondary circuit protection is accomplished with a high voltage diode and simple carbon composition resistor. Circuit disconnect is accomplished with a medium voltage SCR for ringing and loop testing the subscriber line. The battery feed control and loop supervisory functions have been realized in a low voltage, linear integrated circuitry using CBIC technology. View full abstract»

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  • An optically-coupled crosspoint array with high dv/dt capability and high gate sensitivity

    Page(s): 286 - 293
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    A 2/spl times/4 optically-coupled economical crosspoint array for the telephone speech path with a high breakover voltage (>450 V), high dv/dt capability (>200 V/0.1 /spl mu/s), and high gate sensitivity (<5 mA) is described. This has been achieved by a new device structure with a double-gate MOSFET and RC discharge circuitry formed on a p-n-p-n element. This MOS associated circuitry for dv/dt improvement is referred to as `MAC' p-n-p-n elements with MAC can be separated from each other with a new simple isolation technique called `canal isolation' which facilitates low manufacturing cost. Both p-n-p-n elements and LEDs are bonded face-down on a 44 pin chip carrier ceramic package with bump electrodes which again allows low manufacturing cost. The MAC enables independent control of the dv/dt capability and the gate sensitivity. The authors show the MAC performance in dv/dt improvement and various evaluations of MAC, including computer simulation. High breakover voltage technology and some processes for forming the gate-to-cathode resistor R/SUB GK/ for devices with MAC are discussed. This new optically-coupled crosspoint array with MAC makes possible a high-performance direct interface with conventional telephone sets. View full abstract»

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  • A 144 crosspoint switching matrix

    Page(s): 293 - 301
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    The description of this matrix and a discussion of the technology choices are presented. Packaged on a 25 mm square ceramic module, the 4.3/spl times/4.1 mm chip uses a junction isolation crosspoint design fully electrically compatible with its predecessor single-chip crosspoint. A ver low (3/spl times/10/SUP -4/) fraction of the device current is diverted to ground. This is obtained without any additional semiconductor processing steps. Matrix configurations using up to 144 crosspoints are defined by personalization wiring of 2 layers of metal. By comparison with the single crosspoint chip, the additional insertion loss is shown to be negligible and the crosstalk attenuation is improved. On a 760 telephone line system using these chips in a one-wire unbalanced network, the authors measured across the 300-4000 Hz band a maximum insertion loss of 1 dB and a crosstalk of 78 dB (at 4000 Hz) for the worst path and 87 dB for a typical path. View full abstract»

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  • A single-chip CMOS filter/codec

    Page(s): 302 - 307
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    A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics. View full abstract»

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  • A single-chip CMOS PCM codec with filters

    Page(s): 308 - 315
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    A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction. View full abstract»

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  • A single-chip codec with switched-capacitor filters

    Page(s): 315 - 321
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    A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements. View full abstract»

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  • An integrated single-chip PCM voice codec with filters

    Page(s): 322 - 333
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    A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail. View full abstract»

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  • A channel unit signal controller for shared codec D-type channel banks

    Page(s): 341 - 348
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    The channel unit signal controller is a 2.56 mm/spl times/2.56 mm beam-leaded silicon integrated circuit fabricated using the complementary bipolar integrated circuit (CBIC) technology with buried injector logic (BIL). The circuit handles the distribution of signals within a channel unit of a digital telecommunications system. Several diverse circuit functions are incorporated on this device including high-speed emitter-coupled logic, lower speed buried injector logic. JFET switches, high-speed pulse amplifiers to drive the JFETs, a voltage limiter, and a comparator circuit. The channel unit signal controller is described from system and circuit points of view and the CBIC/BIL process is described. View full abstract»

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  • A CCD wave filter with low sensitivity

    Page(s): 348 - 355
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    Starting with a double terminated Chebyshev LC ladder filter, a CCD wave filter has been implemented by using CCD resonators and charge amplifiers as basic building blocks. The bandpass filter which was realized on a test chip has a center frequency of 50 kHz, together with a relative Chebyshev bandwidth of 2.6 percent, 5 dB insertion loss, and more than 60 dB stopband attenuation. Compared to known SC filters, the advantages of the new approach are in extremely low sensitivity of the center frequency which is controlled by an external clock frequency, and a relative bandwidth which does not depend on the center frequency, but is controlled by capacitance ratios. Filter design, some aspects related to implementation, and experimental results are described. View full abstract»

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  • A programmable transversal filter for voice-frequency applications

    Page(s): 367 - 372
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    A fully integrated, programmable transversal filter optimized for low-noise, low-power, voice-frequency applications is described. The filter, fabricated with a standard double-poly NMOS process, achieves convolution of an analog input signal with digital tap weightings using a structure with sample-and-hold gates for analog storage and a multiplexed MDAC for multiplication. The design of the filter eliminates fixed pattern noise usually associated with such structures and enables a dynamic range in excess of 70 dB (LPF, f/SUB o//f/SUB s/=0.08) to be achieved at an 8 kHz sampling rate with a power dissipation of less than 80 mW. This area efficient device forms the basis for a range of possible voice-band signal processing functions. View full abstract»

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  • A single-chip digital signal processor for telecommunication applications

    Page(s): 372 - 376
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    A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques. View full abstract»

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  • A CMOS pipelined single channel digital echo canceller

    Page(s): 377 - 379
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    Recent advances in LSI/VLSI have made the integration of digital echo cancellers both feasible and economical. The design presented features a universal CMOS ALU which is capable of direct I/O with /spl mu/-law encoded data. The ALU is pipelined to achieve high processing speed with low power dissipation. Based on this /spl mu/-law ALU, a 128-tap CMOS pipelined single channel digital echo canceller was designed and simulated, and a prototype was built. Experimental results for a 4 kHz sampling rate are presented. View full abstract»

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  • A broad-band VHF mixer exhibiting high image rejection over a multidecade baseband frequency range

    Page(s): 385 - 392
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    Image-suppressing frequency converters operating over greater than octave RF and LO input bandwidths in the VHF frequency range are described. The devices, designed for RF to video conversion, exhibit very flat conversion loss response and greater than 34 dB rejection of the undesired sideband at any baseband frequency between 186 kHz and 50 MHz. View full abstract»

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  • A three-level broad-banded monolithic analog multiplier

    Page(s): 392 - 399
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    A low-frequency describing function and distortion analysis of a three-level four-quadrant monolithic analog multiplier (mixer) is presented. Expressions are derived for both the conversion `gain' of the down-converted output signal and the amplitudes of the dominant output frequencies. The experimental results presented for a monolithic realization of the proposed mixer reveal its capability to process signals whose frequencies extend through the L-band (1575 MHz). View full abstract»

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  • A voltage-controlled switched-capacitor relaxation oscillator

    Page(s): 412 - 414
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    A new switched-capacitor (SC) oscillator is described. The oscillator is easily modified to be either voltage controlled or digitally programmed. Although the oscillator is practical only when its oscillating frequency is less than about 1/25 the clock frequency (because of the excess phase jitter that develops at higher ratios), it is useful in a number of low frequency applications, especially when stability is important. View full abstract»

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  • [Back inside cover - August 1981]

    Page(s): b1
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    Freely Available from IEEE
  • Multistage negative-resistance amplifier circuit design using nonideal circulators

    Page(s): 400 - 406
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    Using a broadband equivalent circuit of a lossy, nonideal circulator, single-stage and multistage negative-resistance amplifier circuits are studied to determine the effect of circulators and isolators on performance. It is found that feedback phenomena controlled by circuit phase shifts play an important part in determining the amplifier response. View full abstract»

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  • Computer simulation of a voltage standard using multiple Josephson junctions

    Page(s): 407 - 411
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    A multiple junction voltage cell has been computer modeled to test its freedom from spurious internal oscillations and its tolerance to process variations during fabrication. This multiple junction cell model consists of two Josephson junctions coupled together through realistic circuit elements and tied to an external RF source by means of a resistive stripline. Process variations are modeled by varying the values of the shunting resistors and the critical currents of the junctions. This modeling shows stability for the multiple cell structure under realistic circuit values and parameter variances. Resistor variances (peak-to-peak variation) of plus and minus 30 percent still allow a constant voltage step to superimpose across the multiple junction standard. Critical current variances are even less degrading than resistor variances. View full abstract»

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  • CMOS LSI family for the digital communication network

    Page(s): 356 - 362
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    Describes a digital filter LSI, an elastic store LSI, and a frame aligner LSI, which have been added to the CMOS LSI family. The new LSI circuits are made from the 3 μm CMOS technology. They can be applied universally to the first and second levels of PCM hierarchy, contributing significantly to the development of a digital communication network. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan