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IEEE Journal of Solid-State Circuits

Issue 4 • Date Aug. 1981

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Displaying Results 1 - 25 of 32
  • [Front cover - August 1981]

    Publication Year: 1981, Page(s):f1 - b2
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    Freely Available from IEEE
  • [Inside front cover - August 1981]

    Publication Year: 1981, Page(s): f2
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    Freely Available from IEEE
  • Introduction [to the Special Issue]

    Publication Year: 1981, Page(s):245 - 246
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB)

    This is the second special issue on telecommunication circuits to be published in the IEEE Journal of Solid-State Circuits. Since the first was published in February 1979, there have been many advances in ICs for both switching and transmission systems. This issue starts with two overview papers and then presents five groups of papers describing integrated circuits for subscriber-line interfacing ... View full abstract»

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  • A high-voltage IC for a transformerless trunk and subscriber line interface

    Publication Year: 1981, Page(s):261 - 266
    Cited by:  Papers (10)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1039 KB)

    A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration i... View full abstract»

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  • A monolithic subscriber line interface circuit [in bipolar technology]

    Publication Year: 1981, Page(s):266 - 270
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (746 KB)

    A monolithic SLIC fabricated with high-voltage dielectric isolation (DI) technology has been proven to have excellent performance and requires a minimum of external circuitry. The SLIC provides battery feed, overvoltage protection (with some external devices), ringing control, supervision, and hybrid functions. View full abstract»

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  • A monolithic telephone subscriber loop interface circuit

    Publication Year: 1981, Page(s):270 - 278
    Cited by:  Papers (6)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1451 KB)

    An integrated circuit that interfaces a subscriber loop with the digital telephone exchange has been produced with conventional high-voltage IC technology. The monolithic SLIC controls DC loop current, converts signal transmission from two-wire to four-wire, and suppresses longitudinal induction. Bias control circuitry automatically reduces standby power when subscriber equipment is detected on-ho... View full abstract»

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  • A floating, low-power subscriber line interface circuit [bipolar IC technology]

    Publication Year: 1981, Page(s):279 - 285
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1099 KB)

    A subscriber line interface circuit is described which is smaller than and dissipates substantially less heat than conventional circuits which perform similar functions. Worst case heat dissipation in the circuit is only 0.65 W as compared to conventional arrangements which dissipate up to 4 W. The battery feed function is accomplished by a small 1.5 W DC-to-DC converter which also includes circui... View full abstract»

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  • An optically-coupled crosspoint array with high dv/dt capability and high gate sensitivity

    Publication Year: 1981, Page(s):286 - 293
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1421 KB)

    A 2/spl times/4 optically-coupled economical crosspoint array for the telephone speech path with a high breakover voltage (>450 V), high dv/dt capability (>200 V/0.1 /spl mu/s), and high gate sensitivity (<5 mA) is described. This has been achieved by a new device structure with a double-gate MOSFET and RC discharge circuitry formed on a p-n-p-n element. This MOS associated circuitry for ... View full abstract»

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  • A 144 crosspoint switching matrix

    Publication Year: 1981, Page(s):293 - 301
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1373 KB)

    The description of this matrix and a discussion of the technology choices are presented. Packaged on a 25 mm square ceramic module, the 4.3/spl times/4.1 mm chip uses a junction isolation crosspoint design fully electrically compatible with its predecessor single-chip crosspoint. A ver low (3/spl times/10/SUP -4/) fraction of the device current is diverted to ground. This is obtained without any a... View full abstract»

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  • A single-chip CMOS filter/codec

    Publication Year: 1981, Page(s):302 - 307
    Cited by:  Papers (8)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1158 KB)

    A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics. View full abstract»

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  • A single-chip CMOS PCM codec with filters

    Publication Year: 1981, Page(s):308 - 315
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB)

    A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the ch... View full abstract»

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  • A single-chip codec with switched-capacitor filters

    Publication Year: 1981, Page(s):315 - 321
    Cited by:  Papers (12)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB)

    A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements. View full abstract»

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  • An integrated single-chip PCM voice codec with filters

    Publication Year: 1981, Page(s):322 - 333
    Cited by:  Papers (12)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1797 KB)

    A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl pl... View full abstract»

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  • A channel unit signal controller for shared codec D-type channel banks

    Publication Year: 1981, Page(s):341 - 348
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1273 KB)

    The channel unit signal controller is a 2.56 mm/spl times/2.56 mm beam-leaded silicon integrated circuit fabricated using the complementary bipolar integrated circuit (CBIC) technology with buried injector logic (BIL). The circuit handles the distribution of signals within a channel unit of a digital telecommunications system. Several diverse circuit functions are incorporated on this device inclu... View full abstract»

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  • A CCD wave filter with low sensitivity

    Publication Year: 1981, Page(s):348 - 355
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1383 KB)

    Starting with a double terminated Chebyshev LC ladder filter, a CCD wave filter has been implemented by using CCD resonators and charge amplifiers as basic building blocks. The bandpass filter which was realized on a test chip has a center frequency of 50 kHz, together with a relative Chebyshev bandwidth of 2.6 percent, 5 dB insertion loss, and more than 60 dB stopband attenuation. Compared to kno... View full abstract»

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  • A programmable transversal filter for voice-frequency applications

    Publication Year: 1981, Page(s):367 - 372
    Cited by:  Papers (16)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1138 KB)

    A fully integrated, programmable transversal filter optimized for low-noise, low-power, voice-frequency applications is described. The filter, fabricated with a standard double-poly NMOS process, achieves convolution of an analog input signal with digital tap weightings using a structure with sample-and-hold gates for analog storage and a multiplexed MDAC for multiplication. The design of the filt... View full abstract»

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  • A single-chip digital signal processor for telecommunication applications

    Publication Year: 1981, Page(s):372 - 376
    Cited by:  Papers (21)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order f... View full abstract»

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  • A CMOS pipelined single channel digital echo canceller

    Publication Year: 1981, Page(s):377 - 379
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB)

    Recent advances in LSI/VLSI have made the integration of digital echo cancellers both feasible and economical. The design presented features a universal CMOS ALU which is capable of direct I/O with /spl mu/-law encoded data. The ALU is pipelined to achieve high processing speed with low power dissipation. Based on this /spl mu/-law ALU, a 128-tap CMOS pipelined single channel digital echo cancelle... View full abstract»

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  • A broad-band VHF mixer exhibiting high image rejection over a multidecade baseband frequency range

    Publication Year: 1981, Page(s):385 - 392
    Cited by:  Papers (23)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1514 KB)

    Image-suppressing frequency converters operating over greater than octave RF and LO input bandwidths in the VHF frequency range are described. The devices, designed for RF to video conversion, exhibit very flat conversion loss response and greater than 34 dB rejection of the undesired sideband at any baseband frequency between 186 kHz and 50 MHz. View full abstract»

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  • A three-level broad-banded monolithic analog multiplier

    Publication Year: 1981, Page(s):392 - 399
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (990 KB)

    A low-frequency describing function and distortion analysis of a three-level four-quadrant monolithic analog multiplier (mixer) is presented. Expressions are derived for both the conversion `gain' of the down-converted output signal and the amplitudes of the dominant output frequencies. The experimental results presented for a monolithic realization of the proposed mixer reveal its capability to p... View full abstract»

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  • A voltage-controlled switched-capacitor relaxation oscillator

    Publication Year: 1981, Page(s):412 - 414
    Cited by:  Papers (39)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB)

    A new switched-capacitor (SC) oscillator is described. The oscillator is easily modified to be either voltage controlled or digitally programmed. Although the oscillator is practical only when its oscillating frequency is less than about 1/25 the clock frequency (because of the excess phase jitter that develops at higher ratios), it is useful in a number of low frequency applications, especially w... View full abstract»

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  • [Back inside cover - August 1981]

    Publication Year: 1981, Page(s): b1
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    Freely Available from IEEE
  • Interface LSIs for data terminals and facsimile

    Publication Year: 1981, Page(s):362 - 372
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    Describes three high-performance interface LSIs, namely, the facsimile modem, universal receiver transmitter, and code converter LSIs, for facsimile, for communication control equipment, and for a digital service unit to connect the terminal equipment and the network. It is explained that optimization in block partitioning and common use of building block cells has been chosen as the LSI design me... View full abstract»

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  • VLSI technology for telecommunication ICs

    Publication Year: 1981, Page(s):253 - 260
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    The majority of integrated circuits used in telecommunication applications involves a mix of analog and digital functions. Of the available silicon integrated circuit technologies NMOS, CMOS, and I/SUP 2/L/bipolar appear to be the most suitable for these applications since they can provide low power operation as well as high functional density analog and digital circuits on the same chip. The auth... View full abstract»

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  • Computer simulation of a voltage standard using multiple Josephson junctions

    Publication Year: 1981, Page(s):407 - 411
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A multiple junction voltage cell has been computer modeled to test its freedom from spurious internal oscillations and its tolerance to process variations during fabrication. This multiple junction cell model consists of two Josephson junctions coupled together through realistic circuit elements and tied to an external RF source by means of a resistive stripline. Process variations are modeled by ... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com