By Topic

IEEE Journal of Solid-State Circuits

Issue 3 • June 1981

Filter Results

Displaying Results 1 - 25 of 26
  • [Inside front cover - June 1981]

    Publication Year: 1981, Page(s): f2
    Request permission for commercial reuse | PDF file iconPDF (149 KB)
    Freely Available from IEEE
  • Table of contents (June 1981)

    Publication Year: 1981, Page(s): 117
    Request permission for commercial reuse | PDF file iconPDF (119 KB)
    Freely Available from IEEE
  • Foreword: Special Issue on the Sixth European Solid-State Circuits Conference

    Publication Year: 1981, Page(s):118 - 119
    Request permission for commercial reuse | PDF file iconPDF (235 KB)
    Freely Available from IEEE
  • A new charge routing filter

    Publication Year: 1981, Page(s):120 - 124
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1013 KB)

    A fully integrated recursive charge transfer multibridge filter (MBF) is described using the concept of passive recirculation of charges. This is a novel solution for voice channel filters in digital communications. The MBF is constituted of a recursive routing structure and of a split electrode array. The structure behavior is investigated in terms of its state variables. Preliminary experimental... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated seventh-order unit element filter in VIS-SC technique

    Publication Year: 1981, Page(s):140 - 146
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1031 KB)

    Describes a seventh-order unit element switched-capacitor filter based on the voltage invertor switches-switched capacitor (VIS-SC) concept. The operation of this filter is described in detail. It is shown that the effect of parasitic bottom plate capacitances can be overcome by using a special type of VIS. The influence of the top plate parasitics on the filter properties is discussed. Experiment... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 5-bit building block for 20 MHz A/D converters

    Publication Year: 1981, Page(s):151 - 155
    Cited by:  Papers (17)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (866 KB)

    Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conver... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated speech synthesizer

    Publication Year: 1981, Page(s):163 - 168
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (925 KB)

    A large scale integrated speech synthesizer is described. It is based on linear predictive coding which is a voice compression technique. The speech synthesizer is suitable for a wide range of applications, particularly in the telecommunications field. The circuit has been designed and fabricated in standard NMOS silicon-gate enhancement-depletion technology. The multidrain MOS (MDMOS) technique u... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A two-chip imaging system for OCR applications

    Publication Year: 1981, Page(s):168 - 174
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1290 KB)

    Presents a two chip imaging system for optical character recognition (OCR) applications. It consists of a 64/spl times/24 photodiode array providing directly a binary pattern. The image quality is enhanced by means of a separate signal processing chip which performs centering of the image and delivers control signals for further on-line character recognition. The two chips are part of a fully inte... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 16-bit self-testing multiplier

    Publication Year: 1981, Page(s):174 - 179
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1153 KB)

    A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This reali... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An NMOS dual-mode digital low-pass filter for color TV

    Publication Year: 1981, Page(s):179 - 182
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (635 KB)

    A low-pass filter for separation of the luminance and chroma spectra is dealt with. The function of the filter and the implementation of the filter on a chip are briefly described and the circuit design is discussed in some detail. The chip, which runs at frequencies up to 40 MHz, has been designed with two-phase race-compensated MOS logic in a 4 /spl mu/m E/D NMOS technology with implanted underc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An MOS integrated circuit for digital filtering and level detection

    Publication Year: 1981, Page(s):183 - 190
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1274 KB)

    An LSI circuit for digital signal processing has been designed and manufactured in 5 V n-channel MOS technology. Its main functions are to implement digital filters of the cascaded biquadratic form and to perform level detection operations. The frequency response of the filter is controlled by coefficients supplied from an external memory. The device, known by the acronym FAD (filter and detect), ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1.5 V 1 K-CMOS-RAM with only 8 pins

    Publication Year: 1981, Page(s):190 - 194
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (895 KB)

    A 256-bit/spl times/4-bit static RAM working on a supply voltage down to 1.2 V is described. A serial interface for the address and the data with a 4-bit bus reduces the pincount of the RAM to only 8. Special design techniques to reach the design goal-very low power at a reasonable circuit speed-are discussed in detail. The device is fabricated in a low power silicon gate CMOS process. An operatin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.5 V single-supply one-transistor CMOS EEPROM

    Publication Year: 1981, Page(s):195 - 200
    Cited by:  Papers (16)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    Describes a 1.5 V single-supply one-transistor p-channel CMOS EEPROM array which is fabricated with a double polysilicon gate 7-mask CMOS technology. Avalanche injection and Fowler-Nordheim emission are used as very low power programming mechanisms. A thin oxide of 28 nm allows write and erase voltages below -30 V. They are generated on-chip by voltage multipliers and fed by 1.5 V logic circuitry ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated MSI crosspoint array

    Publication Year: 1981, Page(s):205 - 211
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (994 KB)

    A 144-element array of crosspoint switches has been fabricated. With a total insertion loss of 0.04 dB on a 600 /spl Omega/ load and an off state capacitance of 0.4 pF the chip can be used in large switching systems. The crosspoint has a breakdown voltage of 40 V, a holding current of 800 /spl mu/A. A good immunity against transient pulses is achieved by a high dynamic breakdown: typically 3.5 V/n... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A coplanar CMOS power switch

    Publication Year: 1981, Page(s):212 - 226
    Cited by:  Papers (8)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1913 KB)

    A 300 V power switch in a high-voltage CMOS technology compatible with a low-voltage MOS/bipolar technology is presented. This circuit can switch positive and negative 150 V pulses with rise and fall times of 100 ns for a 200 pF capacitive load. The switch has a low-voltage input control (/spl plusmn/15 V). Using earth-symmetrical non-overlapping high-voltage pulses as dynamic supply voltages, it ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Integrated Gamma Corrector

    Publication Year: 1981, Page(s):238 - 241
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    An integrated circuit realizing the nonlinear transfer function Y= X/sup gamma/(gamma = 0.2 · · · 1) is presented. This circuit, especially intended for processing video signals with frequencies up to 6 MHz, features easy adjustment of gamma. A video clamp circuit has been integrated on the chip as well to provide a great flexibility to the user. A great field of application can be ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back inside cover - June 1981]

    Publication Year: 1981, Page(s): b1
    Request permission for commercial reuse | PDF file iconPDF (153 KB)
    Freely Available from IEEE
  • The Development of CCD Analog TV Line Stores

    Publication Year: 1981, Page(s):235 - 238
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    This correspondence discusses the development of analog TV line stores with very low spatial noise and wide signal bandwidth. These devices are fabricated on a buried n-channel silicon gate process which exhibits low thermal leakage and low leakage spike density. A 768-stage and an 850-stage store have been designed. The problems which have been encountered during the development and their solutio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Successive approximation analog-to-digital conversion at video rates

    Publication Year: 1981, Page(s):147 - 151
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    Preliminary work on monolithic successive approximation analog-to-digital converters operating in the video speed range is described. Details of operation of the eight and ten bit digital-to-analog (D/A) converters are presented, with a description of the function of the complementary successive approximation registers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Data Processing Section for Microprocessor-Like Integrated Circuits

    Publication Year: 1981, Page(s):233 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    A methodology for the design of complex logic VLSI circuits is presented. The target application is described by an algorithm from which the structures of the control section and the data processing section of the integrated circuit are inferred. The architectural aspects are discussed and a model is proposed. A set of functional cells is then presented which implements the data section. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Magnetic bubble memory linear interface circuits

    Publication Year: 1981, Page(s):200 - 204
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    Two bipolar integrated circuits are described which provide the write and sense functions required by magnetic bubble memory systems, both organized in four-channel format to minimize board area occupied. The write driver circuit has a 300 mA drive capability and includes on-chip circuitry which prevents fusing of the delicate bubble `hairpin' structure under fault conditions. The sense amplifier ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Charge redistribution codec

    Publication Year: 1981, Page(s):155 - 163
    Cited by:  Papers (3)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1352 KB)

    A charge redistribution codec fabricated by NMOS technology is presented which uses only one capacitor array, thereby resulting in improved accuracy, speed, and chip area utilization. The realization of this scheme requires precision voltage references which are described. A description of a codec complete with logic to interface a full duplex PCM link is included. The chip has provision for async... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

    Publication Year: 1981, Page(s):226 - 232
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabric... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Passive CCD resonator filters

    Publication Year: 1981, Page(s):125 - 129
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    Novel passive recursive CCD bandpass filters have been realized using standard two-level-polysilicon gate NMOS technology. A Chebyshev bandpass (w/SUB rel,/ /SUB 3/ /SUB dB/=3.1 percent) and a fully integrated CCD signal filter with an extremely narrow 3 dB bandwidth of 97 Hz (Q=1350) at 131.85 kHz center frequency were implemented by means of cascaded CCD resonators. The latter chip contains the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Passive CCD resonators [for high Q bandpass filters]

    Publication Year: 1981, Page(s):130 - 135
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    The passive CCD resonator is a recursive CCD building block which is well suited for the realization of high Q bandpass filters. Its realization is compatible with the standard double-poly NMOS technology. Advantages of the new approach are an extremely low sensitivity of the center frequency which is determined by an external clock frequency, a relative bandwidth which does not depend on the cent... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com