IEEE Journal of Solid-State Circuits

Issue 5 • Oct. 1980

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  • [Inside front cover - October 1980]

    Publication Year: 1980, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (October 1980)

    Publication Year: 1980, Page(s): 793
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    Freely Available from IEEE
  • Foreword - Special Issue on Digital Circuits

    Publication Year: 1980, Page(s):794 - 795
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    Freely Available from IEEE
  • Current regulators for I/sup 2/L circuits to be operated from low-voltage power supplies

    Publication Year: 1980, Page(s):796 - 799
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (601 KB)

    A new bandgap current reference is described which can be used to control the injector current of I/SUP 2/L circuits for supply voltages down to about 1 V. For small currents the total injector current is obtained as a mirror of the reference current. For large injector currents the current control is performed by a series regulator which compares the injector current of one I/SUP 2/L gate to the ... View full abstract»

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  • A 400 ps bipolar 18 bit RALU using advanced PSA

    Publication Year: 1980, Page(s):802 - 808
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1057 KB)

    Describes a bipolar 18 bit register arithmetic logic unit (RALU) with 1300-gate complexity using an advanced bipolar process named Advanced PSA (APSA). The high-performance of the Advanced PSA transistor has made it possible to achieve a 400 ps delay time with 2.5 mW for a basic low level CML (LCML) circuit. The read-modify-write cycle time is 7 ns in an 18-bit ALU operation. Furthermore, with fou... View full abstract»

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  • A gigabit MOS logic circuit with buried channel MOSFETs

    Publication Year: 1980, Page(s):809 - 816
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1535 KB)

    An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m... View full abstract»

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  • A 50K bit Schottky cell bipolar read-only memory

    Publication Year: 1980, Page(s):816 - 820
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (774 KB)

    Describes a 50K bit read-only memory (ROM) which is used on a 7.00 mm square chip. The ROM occupies 2.53 mm/spl times/6.37 mm. The worst case access time is 36 ns and worst case power dissipation is 650 mW. Power supplies of 5.0 V/spl plusmn/10 percent and 1.7 V/spl plusmn/10 percent are required. A description of the ROM organization and operation is given and each of the individual circuits is d... View full abstract»

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  • An on-chip back-bias generator for MOS dynamic memory

    Publication Year: 1980, Page(s):820 - 826
    Cited by:  Papers (14)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1178 KB)

    An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger ... View full abstract»

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  • A high performance sense amplifier for a 5 V dynamic RAM

    Publication Year: 1980, Page(s):831 - 839
    Cited by:  Papers (10)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1375 KB)

    Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing ... View full abstract»

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  • A 100 ns 5 V only 64Kx1 MOS dynamic RAM

    Publication Year: 1980, Page(s):839 - 846
    Cited by:  Papers (10)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1313 KB)

    A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL ... View full abstract»

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  • A 5 V-only 64K dynamic RAM based on high S/N design

    Publication Year: 1980, Page(s):846 - 854
    Cited by:  Papers (51)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1353 KB)

    A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule. The design features of this dynamic RAM are described. In particular, memory cell and S/N (signal/noise) designs are focused of a dynamic RAM with an on-chip bias generator. The device fabricated provides a typical access time of 120 ns and a 170 mW operating power, with mini... View full abstract»

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  • An 8Kx8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

    Publication Year: 1980, Page(s):854 - 861
    Cited by:  Papers (10)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1520 KB)

    A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and ph... View full abstract»

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  • An 18K bipolar dynamic random access memory

    Publication Year: 1980, Page(s):861 - 865
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A 2K/spl times/9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75 ns and 300 ns access and cycle time, respectively. The design is based on a two device cell of 800 /spl mu/m/SUP 2/ size. All chip input and output signals are TTL compatible. View full abstract»

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  • A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

    Publication Year: 1980, Page(s):865 - 872
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1565 KB)

    Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patt... View full abstract»

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  • A 256K bit dynamic RAM

    Publication Year: 1980, Page(s):872 - 874
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (473 KB)

    A 256K/spl times/1 bit NMOS dynamic RAM, fabricated using conventional n-channel two-layer polysilicon gate technology, is described. The memory cell was laid out in 5.7 /spl mu/m/spl times/12.5 /spl mu/m, and the die measured 4.84 mm/spl times/8.59 mm which can use a standard 300 mil 16 pin DIP. Reduction of the bit line capacitance was accomplished using the second polysilicon layer for the bit ... View full abstract»

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  • A wide-band current-controlled oscillator using bipolar-JFET technology

    Publication Year: 1980, Page(s):872 - 874
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (943 KB)

    A new monolithic current-controlled oscillator, which features a highly linear frequency range of more than seven decades, has been realized in a compatible JFET-bipolar technology. Low current performance is accomplished by the use of two p-channel JFET-source-followers and a special load consisting of a string of diodes driven by a continuous current source. Temperature compensation for frequenc... View full abstract»

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  • All TTL Compatible Clock CCD Memory with CCD Generator

    Publication Year: 1980, Page(s):881 - 886
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1141 KB)

    The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase ... View full abstract»

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  • An Electrically Programmable Split-Electrode Charge-Coupled Transversal Filter (EPSEF)

    Publication Year: 1980, Page(s):899 - 907
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1800 KB)

    A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several ... View full abstract»

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  • Comparative logic figure of merit of current high-speed transistors

    Publication Year: 1980, Page(s):899 - 907
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB)

    A logic figure of merit is used for the comparative measure of speed of three transistors that represent current technology applied to high-speed transistors. An indium phosphide Schottky-barrier field-effect transistor with a channel length of 1 /spl mu/m has T/SUB FM/=69.2 ps. A gallium arsenide field-effect transistor of essentially the same geometry has T/SUB FM/=80.7 ps. A silicon bipolar tra... View full abstract»

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  • [Back inside cover - October 1980]

    Publication Year: 1980, Page(s): b1
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    Freely Available from IEEE
  • Dynamic CMOS amplifiers

    Publication Year: 1980, Page(s):881 - 886
    Cited by:  Papers (64)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1280 KB)

    A family of dynamic CMOS amplifiers is presented and discussed. First, the concept of dynamic circuit is introduced. Then two groups of circuits with different biasing principles are shown, and experimental results are presented. The advantages of dynamic amplifiers are low power consumption, high voltage gain, large bandwidth, and low offset voltages. View full abstract»

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  • Static RAMs with microwatt data retention capability

    Publication Year: 1980, Page(s):826 - 831
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    Static RAMs using undoped polysilicon load resistor cells can retain data at less than a nanowatt/bit. This allows large memories to be designed for low-power battery backup applications provided 1) all peripheral circuits can be powered down without disturbing the stored data, and 2) subthreshold leakages of `off' transistors in the memory are at an adequately low level to maintain the stored dat... View full abstract»

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  • Modeling of a nonpinchoff depletion mode MOSFET

    Publication Year: 1980, Page(s):887 - 894
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A depletion-mode MOSFET is typically formed with a thin channel of opposite conductivity type to the substrate. When a large gate voltage is applied to deplete this channel, an inversion layer is induced. As strong inversion occurs, the depletion layer depth reaches a maximum and cannot be further increased. If this depth is less than the thickness of the channel, the channel cannot be pinched off... View full abstract»

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  • Oxide-isolated integrated Schottky logic

    Publication Year: 1980, Page(s):800 - 802
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 μm lines and spaces. The novel device uses a merged substrate p-n-p (base width ≃1.0 μm) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation del... View full abstract»

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  • The response of 741 op amps to very short pulses

    Publication Year: 1980, Page(s):908 - 910
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A 741 op amp behaves like a monostable multivibrator when very short pulses are applied to the noninverting input terminal. It is shown that perturbations on the power supply lines or at the output of the amplifier will directly or indirectly have the same effect on the op amp. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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