By Topic

Solid-State Circuits, IEEE Journal of

Issue 3 • Date June 1980

Filter Results

Displaying Results 1 - 25 of 30
  • [Inside front cover - June 1980]

    Page(s): f2
    Save to Project icon | Request Permissions | PDF file iconPDF (110 KB)  
    Freely Available from IEEE
  • Table of contents (June 1980)

    Page(s): 261
    Save to Project icon | Request Permissions | PDF file iconPDF (79 KB)  
    Freely Available from IEEE
  • Editor's Note (June 1980)

    Page(s): 262
    Save to Project icon | Request Permissions | PDF file iconPDF (66 KB)  
    Freely Available from IEEE
  • Guest Editorial - Special Issue on the Fifth European Solid-State Circuits Conference (ESSCIRC)

    Page(s): 262 - 263
    Save to Project icon | Request Permissions | PDF file iconPDF (221 KB)  
    Freely Available from IEEE
  • MOS voltage reference based on polysilicon gate work function difference

    Page(s): 264 - 269
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A GaAs MESFET sample and hold switch [for video A/D conversion]

    Page(s): 282 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1029 KB)  

    A monolithic GaAs MESFET sample and hold switch has been designed, primarily as a research vehicle for GaAs linear integrated circuit technology. A novel FET-ring circuit configuration has been used in order to overcome the problems associated with switch drive in more conventional circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A true logarithmic amplifier for radar IF applications

    Page(s): 291 - 295
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (633 KB)  

    There are certain radar receivers where the settling time of an AGC loop is unacceptable and an amplifier is required which will compress the dynamic range instantaneously. A common technique for accomplishing this is to use a logarithmic amplifier. This has other advantages in radar applications in that a logarithmic amplifier can assist in separating wanted signals from unwanted signals known as `clutter' caused by unwanted targets such as raindrops. In systems such as MTI radar systems, where it is required to detect moving targets, the phase information is important hence the logarithmic output must be at the IF frequency. In order to preserve the phase information the phase shift or delay through the log amplifier should not vary with input signal level. This type of amplifier is known as a true logarithmic amplifier. The device described in this paper is capable of producing a true logarithmic amplifier with phase matching of /spl plusmn/4/spl deg/ over an 80 dB input dynamic range at 70 MHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed NMOS A/D converter with a current source array

    Page(s): 295 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1333 KB)  

    A high-speed MOS analog-to-digital (A/D) converter has been designed and fabricated in a standard single channel metal-gate enhancement/depletion MOS process. The use of current switching performs a conversion time of 13.2 /spl mu/s at a resolution of 8 bits. To replace the resistance ladder a binary weighted current source array has been implemented which consists of MOS transistors. The test circuit requires 4 mm/SUP 2/ including all analog circuit functions without the successive approximation register. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A synchronous switched capacitor filter [CMOS Si-gate implementation]

    Page(s): 301 - 305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (725 KB)  

    A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experimental circuit has been implemented in CMOS Si-gate technology with a programmable gain of 20 dB and 40 dB, corresponding to a Q factor of 8.6 and 79, respectively. Experimental results are in good agreement with the theory. Modifications of the basic circuit are proposed to cancel the effects of parasitic capacitances and to reduce the chip area. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed ECL 100K compatible 64x4 bit RAM with 6 ns access time

    Page(s): 306 - 305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (741 KB)  

    An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 8K EEPROM using the SIMOS storage cell

    Page(s): 311 - 315
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (858 KB)  

    An 8192 bit MOS floating-gate EEPROM has been developed and transferred to volume production. The memory uses a two-transistor SIMOS cell for nonvolatile storage of alterable data. The cell is programmed by channel injection of hot electrons while electrical erasure is achieved by tunneling of cold electrons through a thin oxide. Standard production parts show a minimum endurance of 10/SUP 3/ program-erase cycles. The extrapolated data retention is at least 10 years of operation in a 70/spl deg/C ambient, while the number of read cycles is unlimited. Cell design features provide reliable programming combined with minimum sensitivity to fabrication tolerances. Special circuit design, however, ensures programmability of deeply erased cells and avoids electrical stress to the cell unintentionally affecting the programmed information. A novel read amplifier design allowed the realization of an access time of less than 350 ns. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis and characterization of the depletion-mode IGFET

    Page(s): 331 - 340
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (997 KB)  

    Using simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET. Various conditions which can coexist at the surface, such as accumulation, depletion, and inversion, are taken into account. The implanted channel is approximated by a box profile. The basic model elements, namely, the source-drain transport current and the various charging currents, are explicitly given in terms of known processing data and implanted channel parameters. Device threshold voltage, drain saturation voltage, and conditions for surface inversion are explicitly given as a function of these parameters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computer analysis and modeling of injection-coupled synchronous logic (ICSL) gates

    Page(s): 340 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB)  

    Discusses the computer analysis and modeling of injection-coupled synchronous logic (ICSL) gates. A lumped circuit model is developed taking into account the layout and dimensions of the gate. The model is suitable for analysis using a standard computer program such as SPICE. Equations for the static and dynamic model parameters including partial base currents, collector currents, current gains, transit times, and depletion capacitances are developed in terms of physical dimensions and process parameters. The performance of the model is successfully tested against experimental results over a wide range of injection currents. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

    Page(s): 346 - 353
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1221 KB)  

    A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A two-transistor SIMOS EAROM cell

    Page(s): 353 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB)  

    A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate injection-type MOS (SIMOS) technique. Programming is achieved by two mechanisms: channel injection of hot electrons and field emission. Analysis of experimental data shows that the contribution of the field emission mechanism to programming is significantly high when the memory device operates in the depletion mode. Erase occurs via field emission of electrons from the floating gate through a thin oxide thermally grown on monosilicon to an n/SUP +/-diffusion area placed outside the channel region of the memory transistor. This additional floating gate/n/SUP +/-diffusion overlap is also utilized to increase the programming efficiency by applying a voltage to the n/SUP +/-diffusion terminal in addition to the gate and the drain voltage. This voltage is shown to have a strong influence on the two programming mechanisms. Memory retention compares favorably with that of the most advanced electrically programmable, read-only memory (EPROM) devices. Endurance is limited by charge trapping in the thin erase oxide to approximately 10000 write/erase cycles. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A phototransistor optical isolator noise model

    Page(s): 361 - 365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB)  

    A noise model for the phototransistor optical isolator is presented and used to predict optical isolator noise performance. Results are shown to agree with existing experimental data on phototransistor optical isolator noise. The model presented includes burst noise, flicker noise and shot noise. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An IC temperature transducer with an intrinsic reference

    Page(s): 370 - 373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A new single-chip temperature transducer which produces an output signal on a Fahrenheit, a Celsius, or an arbitrary scale has been designed, manufactured, and tested. This device, which operates with the intrinsic bandgap voltage as reference, can be easily calibrated at ambient temperatures. High accuracy and excellent long-term stability is achieved with simple bipolar circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back inside cover - June 1980]

    Page(s): b1
    Save to Project icon | Request Permissions | PDF file iconPDF (106 KB)  
    Freely Available from IEEE
  • Monolithic components for 100 MHz data conversion [4-bit expandable A/D convertor]

    Page(s): 286 - 290
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (944 KB)  

    Describes a 4 bit expandable analog to digital converter capable of operation at clock rates of over 100 MHz in 8 bit systems under Nyquist limit sampling conditions. Essential to these high speeds are a fast (>5 GHz F/SUB T/) bipolar process and a design approach which takes every advantage of the components available. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fabrication of two independent electrothermal integrators on a single chip [for state-variable filters]

    Page(s): 366 - 368
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    A new layout geometry is given for a rectangular electrothermal circuit (ETC) which produces a single-pole transfer function. Two such circuits, or channels, can be fabricated on a single chip by using an isotropic etch to cut slots which provide isolation between the channels. By addition of appropriate electronic circuits, each channel can be used as an integrator and hence as a building block for a state-variable filter. Measured isolation between channels is 55 dB, and good agreement is obtained between measured and calculated magnitude and phase response of each channel. Good agreement is also obtained between measured and calculated integrator frequency response. Additional external circuitry has been added to produce a bandpass filter with center frequency of 60 Hz and Q of 10; measured and calculated results agree within 3 percent. A new configuration is proposed for integrating on a single chip two ETC integrators and all auxiliary circuits necessary for a second-order filter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effect of alpha-particle-induced soft errors on memory systems with error correction

    Page(s): 319 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    Using Poisson statistics, a model for the survival probability of integrated memory circuits having both hard and soft error bit failure mechanisms is developed. Calculations are made over a range of soft error generation rates and erasure intervals for both single and double error correction. It is shown that even if the soft errors are erased effectively instantaneously, there is still an impact on the probability of system survival which is a function of soft error generation rate, and that in the case of instantaneous erasure of soft errors, a system with N bit error correction will have a probability of survival at least as good as the same system with N-1 bit error correction, no matter how high the soft error generation rate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-voltage DIMOS driver circuit

    Page(s): 328 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    High-voltage output driver circuits realized with double-implanted MOS (DIMOS) transistors are presented. Breakdown voltages exceed 100 V. Dynamic bootstrap techniques resulted in circuits combining low power (5 mW) and fast switching times (150 ns) at typical operating conditions of 5 V/50 V, 50 pF, and 16 kHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Three-dimensional transient thermal simulation: application to delayed short circuit protection in power ICs

    Page(s): 277 - 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    Thermal effects may represent a limiting factor in the development of integrated circuits. As the power dissipated by integrated circuits becomes more relevant, the need increases for accurate modeling of the stationary and transient thermal behavior of the die-package structure. An analytical solution of the three-dimensional transient thermal diffusion problem is presented for a two-layer structure, together with a simple computer program for the calculation of the solution. The program, implemented on a minicomputer, is proven to be fast and accurate. The simulation technique is then applied to the design of a new short-circuit protection of a 6A current booster. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • MACLOS-mask checking logic simulator [for MOS LSI]

    Page(s): 368 - 370
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    A new logic simulator is described which uses the output from a mask analysis program as the input circuit data. Each circuit node is treated as the output of a multiinput transfer gate. Three logical states: 0, 1, and X, and four auxiliary states: D, S, B, and Z, are used in the simulation with a unit gate delay. The circuit node in the E/D MOS LSI is sorted into two types. The one, named TG, looks like the output of a multiinput transfer gate, and the other, named PTG, is like a transfer gate with a pulling-up transistor. MACLOS was successfully applied to a 12-bit microprocessor chip including 10K transistors and a RAM block fabricated by the E/D MOS process. It took 25 min for ACOS 700 to simulate the microprocessor for 213 clock cycles; 49K words of core memory were used in the simulation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unified field-effect transistor theory including velocity saturation

    Page(s): 325 - 328
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    It is shown that in any kind of field-effect transistor structure, the usual gradual channel approximation solutions developed for v=μ/SUB 0/E also hold in a slightly modified form for v=μ/SUB 0/E/|1+(μ/SUB 0/E/v/SUB s/)| which gives a good approximation to the velocity field relationship in silicon FETs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan