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IEEE Journal of Solid-State Circuits

Issue 3 • June 1980

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Displaying Results 1 - 25 of 30
  • [Inside front cover - June 1980]

    Publication Year: 1980, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1980)

    Publication Year: 1980, Page(s): 261
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    Freely Available from IEEE
  • Editor's Note (June 1980)

    Publication Year: 1980, Page(s): 262
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    Freely Available from IEEE
  • Guest Editorial - Special Issue on the Fifth European Solid-State Circuits Conference (ESSCIRC)

    Publication Year: 1980, Page(s):262 - 263
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    Freely Available from IEEE
  • MOS voltage reference based on polysilicon gate work function difference

    Publication Year: 1980, Page(s):264 - 269
    Cited by:  Papers (33)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature com... View full abstract»

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  • A GaAs MESFET sample and hold switch [for video A/D conversion]

    Publication Year: 1980, Page(s):282 - 285
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1029 KB)

    A monolithic GaAs MESFET sample and hold switch has been designed, primarily as a research vehicle for GaAs linear integrated circuit technology. A novel FET-ring circuit configuration has been used in order to overcome the problems associated with switch drive in more conventional circuits. View full abstract»

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  • A true logarithmic amplifier for radar IF applications

    Publication Year: 1980, Page(s):291 - 295
    Cited by:  Papers (19)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (633 KB)

    There are certain radar receivers where the settling time of an AGC loop is unacceptable and an amplifier is required which will compress the dynamic range instantaneously. A common technique for accomplishing this is to use a logarithmic amplifier. This has other advantages in radar applications in that a logarithmic amplifier can assist in separating wanted signals from unwanted signals known as... View full abstract»

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  • A high-speed NMOS A/D converter with a current source array

    Publication Year: 1980, Page(s):295 - 307
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1333 KB)

    A high-speed MOS analog-to-digital (A/D) converter has been designed and fabricated in a standard single channel metal-gate enhancement/depletion MOS process. The use of current switching performs a conversion time of 13.2 /spl mu/s at a resolution of 8 bits. To replace the resistance ladder a binary weighted current source array has been implemented which consists of MOS transistors. The test cir... View full abstract»

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  • A synchronous switched capacitor filter [CMOS Si-gate implementation]

    Publication Year: 1980, Page(s):301 - 305
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (725 KB)

    A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experiment... View full abstract»

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  • A high-speed ECL 100K compatible 64x4 bit RAM with 6 ns access time

    Publication Year: 1980, Page(s):306 - 305
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (741 KB)

    An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circu... View full abstract»

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  • An 8K EEPROM using the SIMOS storage cell

    Publication Year: 1980, Page(s):311 - 315
    Cited by:  Papers (6)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (858 KB)

    An 8192 bit MOS floating-gate EEPROM has been developed and transferred to volume production. The memory uses a two-transistor SIMOS cell for nonvolatile storage of alterable data. The cell is programmed by channel injection of hot electrons while electrical erasure is achieved by tunneling of cold electrons through a thin oxide. Standard production parts show a minimum endurance of 10/SUP 3/ prog... View full abstract»

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  • Analysis and characterization of the depletion-mode IGFET

    Publication Year: 1980, Page(s):331 - 340
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (997 KB)

    Using simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET. Various conditions which can coexist at the surface, such as accumulation, depletion, and inversion, are taken into account. The implanted channel is approximated by a box profile. The basic model elements, namely, the source-drain transport current and the various charging currents, are exp... View full abstract»

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  • Computer analysis and modeling of injection-coupled synchronous logic (ICSL) gates

    Publication Year: 1980, Page(s):340 - 345
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB)

    Discusses the computer analysis and modeling of injection-coupled synchronous logic (ICSL) gates. A lumped circuit model is developed taking into account the layout and dimensions of the gate. The model is suitable for analysis using a standard computer program such as SPICE. Equations for the static and dynamic model parameters including partial base currents, collector currents, current gains, t... View full abstract»

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  • A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

    Publication Year: 1980, Page(s):346 - 353
    Cited by:  Papers (12)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1221 KB)

    A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle lim... View full abstract»

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  • A two-transistor SIMOS EAROM cell

    Publication Year: 1980, Page(s):353 - 357
    Cited by:  Papers (4)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (722 KB)

    A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate injection-type MOS (SIMOS) technique. Programming is achieved by two mechanisms: channel injection of hot electrons and field emission. Analysis of experimental data shows that the contribution of the fiel... View full abstract»

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  • A phototransistor optical isolator noise model

    Publication Year: 1980, Page(s):361 - 365
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB)

    A noise model for the phototransistor optical isolator is presented and used to predict optical isolator noise performance. Results are shown to agree with existing experimental data on phototransistor optical isolator noise. The model presented includes burst noise, flicker noise and shot noise. View full abstract»

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  • An IC temperature transducer with an intrinsic reference

    Publication Year: 1980, Page(s):370 - 373
    Cited by:  Papers (15)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A new single-chip temperature transducer which produces an output signal on a Fahrenheit, a Celsius, or an arbitrary scale has been designed, manufactured, and tested. This device, which operates with the intrinsic bandgap voltage as reference, can be easily calibrated at ambient temperatures. High accuracy and excellent long-term stability is achieved with simple bipolar circuits. View full abstract»

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  • [Back inside cover - June 1980]

    Publication Year: 1980, Page(s): b1
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    Freely Available from IEEE
  • Fabrication of two independent electrothermal integrators on a single chip [for state-variable filters]

    Publication Year: 1980, Page(s):366 - 368
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A new layout geometry is given for a rectangular electrothermal circuit (ETC) which produces a single-pole transfer function. Two such circuits, or channels, can be fabricated on a single chip by using an isotropic etch to cut slots which provide isolation between the channels. By addition of appropriate electronic circuits, each channel can be used as an integrator and hence as a building block f... View full abstract»

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  • Finite amplifier gain and bandwidth effects in switched-capacitor filters

    Publication Year: 1980, Page(s):358 - 361
    Cited by:  Papers (62)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Discusses the effects of finite operational-amplifier gain and bandwidth on the response of the most widely used switched-capacitor filter section. Formulas are derived for the minimum acceptable values of the DC amplifier gain and the unity-gain frequency under specified conditions. View full abstract»

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  • The effect of alpha-particle-induced soft errors on memory systems with error correction

    Publication Year: 1980, Page(s):319 - 325
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    Using Poisson statistics, a model for the survival probability of integrated memory circuits having both hard and soft error bit failure mechanisms is developed. Calculations are made over a range of soft error generation rates and erasure intervals for both single and double error correction. It is shown that even if the soft errors are erased effectively instantaneously, there is still an impact... View full abstract»

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  • Monolithic components for 100 MHz data conversion [4-bit expandable A/D convertor]

    Publication Year: 1980, Page(s):286 - 290
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    Describes a 4 bit expandable analog to digital converter capable of operation at clock rates of over 100 MHz in 8 bit systems under Nyquist limit sampling conditions. Essential to these high speeds are a fast (>5 GHz F/SUB T/) bipolar process and a design approach which takes every advantage of the components available. View full abstract»

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  • MACLOS-mask checking logic simulator [for MOS LSI]

    Publication Year: 1980, Page(s):368 - 370
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A new logic simulator is described which uses the output from a mask analysis program as the input circuit data. Each circuit node is treated as the output of a multiinput transfer gate. Three logical states: 0, 1, and X, and four auxiliary states: D, S, B, and Z, are used in the simulation with a unit gate delay. The circuit node in the E/D MOS LSI is sorted into two types. The one, named TG, loo... View full abstract»

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  • Built-in test for complex digital integrated circuits

    Publication Year: 1980, Page(s):315 - 319
    Cited by:  Papers (110)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on ... View full abstract»

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  • Unified field-effect transistor theory including velocity saturation

    Publication Year: 1980, Page(s):325 - 328
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    It is shown that in any kind of field-effect transistor structure, the usual gradual channel approximation solutions developed for v=μ/SUB 0/E also hold in a slightly modified form for v=μ/SUB 0/E/|1+(μ/SUB 0/E/v/SUB s/)| which gives a good approximation to the velocity field relationship in silicon FETs. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com