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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Feb. 1980

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Displaying Results 1 - 24 of 24
  • [Inside front cover - February 1980]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (February 1980)

    Page(s): 1
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    Freely Available from IEEE
  • Foreword [to the Special Issue]

    Page(s): 2 - 3
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    Freely Available from IEEE
  • A CORDIC Arithmetic Processor Chip

    Page(s): 4 - 15
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    A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addition to the menu of hyperbolic and linear operations, is a relatively trivial matter, in terms of both hardware cost and execution time. A bulk CMOS technology with conservative layout rules is used for the sake of high reliability, low-power consumption, and good cycle speed. View full abstract»

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  • An NMOS Microprocessor for Analog Signal Processing

    Page(s): 33 - 38
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    A special purpose microprocessor for real time processing of analog signals is described. Design and implementation of architecture allowing a user programmable and erasable read only memory (EPROM), a 25 bit digital processor and a 9 bit analog acquisition system on the same substrate is discussed. The relationship between the device's resources and specific signal processing building blocks is discussed. View full abstract»

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  • An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

    Page(s): 38 - 43
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    A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm/sup 2/, out of a total unit area of 35 mm/sup 2/. View full abstract»

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  • An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

    Page(s): 52 - 60
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    Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design. This paper describes a totally unique device-the polynomial generator checker (WC) that monitors transactions on a data bus and performs functions such as programmable character comparisons, parity generation/checking, and "intelligent" block error generation/checking. An overview of character oriented data link controls and cyclic redundancy check/longitudinal redundancy check (CRC/LRC) provides an introduction to the functions and applications of the PGC. Several innovative architectural constructs be described that enable the device to fit within the die cavity of a 16 pin dual-in-like package. View full abstract»

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  • Acceptable Testing of VLSI Components Which Contain Error Correctors

    Page(s): 61 - 70
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    If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes maybe employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thns obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability. View full abstract»

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  • A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic

    Page(s): 70 - 80
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    This paper describes a gesteral-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-order structure is examined. The processor wordlength is 16 bit; its basic cycle time, 300 ns; its data memory size, 2K words; its control store size, 256 x 56 bits. It consumes 48 W of power and has special address processing hardware. Experimental results with a twelfth-order digital filter are demonstrated. The signal processor is also compared with several other signal processors of its class described in the literature. View full abstract»

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  • IEEE copyright form

    Page(s): 149 - 150
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    Freely Available from IEEE
  • [Back inside cover - February 1980]

    Page(s): b1
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    Freely Available from IEEE
  • High Density Integrated Computing Circuitry with Multiple Valued Logic

    Page(s): 127 - 131
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    It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quatemary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case. View full abstract»

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  • Design Considerations for Single-Chip Computers of the Future

    Page(s): 44 - 52
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    In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design. View full abstract»

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  • Modular Minicomputers Using Microprocessors

    Page(s): 85 - 96
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    This paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instuctions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's. The design was aimed at applications with inherent parallelism, such as those employing multiuser interactive or multistream batch processing, and avoided dependencies on problem decomposition per se. Measurements on a breadboard version showed that in suitable batch processing environments, an eight processor system could achieve a throughput that was 6.5 times greater than that of a single component processor. They also showed that on increasing the number of users in interactive environments, the behavior of the mP was similar to that of an uniprocessor of like throughput. However, the response time seen in any given application would betray the speed of the constituent microprocessor relative to that of the uniprocessor, in proportion to the amount of direct processor activity involved in that application. The hardware design included an mP switch element comprised of a time-multiplexed pipeline whose heart was a common cache serving all the processors. The software design was based on minor modifications to an existing real-time multiprogramming OS. Software contention losses due to the global interlock used within the shared single-threaded executive were surprisingly small. This paper contains an extensive discussion on hardware and software contention. It highlights the limitations of the chosen techniques and identifies some environments for which they seem well-suited, as well as some for which they are not. Finally, it indicates areas where more work is needed. View full abstract»

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  • Optimal Interconnections in the Design of Microprocessors and Digital Systems

    Page(s): 81 - 85
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    This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed. View full abstract»

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  • Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

    Page(s): 131 - 135
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    Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Furthermore, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count. View full abstract»

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  • Microprocessor Utilization in Satellite-Born Packet Switching

    Page(s): 142 - 144
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    This correspondence deals with the application of a bit slice microprocessor to a satellite born packet switch. A system architecture for accomplishing this task is proposed, and the performance of the packet switch is evaluated by obtaining an upper bound on the system throughput. View full abstract»

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  • Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System

    Page(s): 15 - 24
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    The binary picture processing and recognizing stages of an optical character recognition (OCR) system have been designed using both flexibility of available microprocessors and speed of peripheral custom-designed integrated circuits, A dedicated Iarge-scale integrated (LSI) processor performs edge detection and thinning of a 32 X 24 digitied one-piece pattern. The output signal-a set of 3 bit vectors describing the skeletonized character contour-feeds a microprocessor which controls the character recognition algorithm including pattern segmentation, filtering, feature extraction, and classification decision. This low-cost equipment is especirdly suitable for hand-carried OCR systems where well-formed printed alphanumerics are to be read: However, continously deformed patterns like carefully handprinted characters are recognized as well. A system reading speed of 100 characters/s (or 30 cm/s) can be achieved. View full abstract»

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  • MOVE Architecture in Digital Controllers

    Page(s): 116 - 126
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    The conditional MOVE processor (CMOVE) has been proposed for replacement of logic table driven sequencers like traffic light controllers and microcomputer I/O processors, in order to take better advantage of hardware-software tradeoffs. Herein the architecture of the CMOVE processor is sketched, and its application to traditional numerical control problems is studied. Two basis types of controllers, of potential use in industrial process control, are taken into account: the digital filter type, expressed as a ratio of two 2-transform polynomials (the proportional-integral-differential (PID) controllers is a particular case of the above), and the matrix multiplication type, which produces a control vector in response to a state vector input. A detailed program for a CMOVE realizatiorn of the digital filter is presented. A number of alternative realizations of the matrix controller are discussed in detail and evatuated. View full abstract»

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  • Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task

    Page(s): 97 - 116
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    Continuing technological advances in single-chip intelligence and storage cell density, and in bulk store performance provide increasing opportunities to construct multiple microprocessor systems. The objective of this experimental study was to explore the performance of selected system architectures in a manner sufficiently detailed, quantitative and realistic to 1) contribute to our understanding of the fundamental behavior of such systems and 2) permit practical designs to follow from the results. Four different classes of system architecture were studied: System I-fully connected; System II-bused with private primary store; System III-bused with both public and private primary store; and System IV-a uniprocessor system. All multiple-processor configurations comprised autonomous computing units which were loosely coupled with parallel links, and performed dedicated functions in a cooperative tasking environment. At the time the study began much of the anticipated technology was not yet available so detailed deterministic models of the systems were developed. All testing was done using a specially developed discrete simulation tool called the System-State Model (SSM). Both hardware and software details, derived from an operational system, were included in each model structure to represent the necessary concurrent, hierarchical, and ranked activity. A basic, interactive data base task was used as the test case. Experimental parameters included number of users, task load, console channel and bulk store channel configurations, and secondary store access time regimes. Over one hundred simulation runs were made which provided both internal and external performance measurements. Analysis of the results revealed a complex set of performance relationships which, in turn, led to several fundamental assessments. These include 1) every configuration can have its performance severely limited by the presence of any one of several key factors, 2) bulk store access time regimes and channel configuration have a critical effect on all system architectures, 3) performance distinctions among systems become more pronounced with increased number of users and with task load, and 4) each of Systems II, III, and IV manifests unique and useful performance ch- aracteristics and could be the configuration of choice under the right conditions. Overall, the results provide detailed confirmation of the utility of such systems and suggest a variety of specific tradeoffs among the architectures. View full abstract»

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  • Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

    Page(s): 138 - 142
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    Microcomputer system reliability using triple-modular redundancy (TMR) is discussed when failures exist not only in any single module but also in any two or three modules at a time. The optimal time interval is calculated by which the system will even be resynchronized periodically so that additional transient failures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU's. View full abstract»

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  • The Development of a Bubble Memory Controller for Low-Cost FiIe Use

    Page(s): 25 - 32
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    The bubble memory has several features such as low-cost low-power consumption, small physical size, high reliability, and non-volatility, which make it suitable for low-cost microcomputer files. The microcomputer interface and bubble control logics are integrated into a single chip which we call the bubble memory controller (BMC), making it possible to install a complete 1 Mbit bubble memory system on a 15 cm X 18 cm board. This paper describes in detail the BMC development and considers important matters in the design of large-scale logic LSI's which are represented by the microprocessors. View full abstract»

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  • Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System

    Page(s): 136 - 138
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    An analog data acquisition system typically consists of an analog multiplexer followed by an analog to digital (A/D) converter. An alternative configuration uses multiple comparators (one per input) followed by a digital multiplexer. If the control functions for A/D conversion are incorporated into a microprocessor, several potentially interesting data acquisition and conversion strategies are available. At first thought, an interrupt-driven conversion process which simultaneously searches all inputs in parallel for a level match appears attractive. However, analysis shows that a sequential conversion of the inputs, one at a time, using the successive approximation algorithm, is usually superior. View full abstract»

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  • MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control

    Page(s): 144 - 147
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    A flexible and modular control system for astronomical telescopes and their associated observational instruments is implemented using an eight-bit microprocessor, and the various design features of a compact single board computer are discussed. A simple message protocol and system of UART serial links is used to achieve modularity and expandability of such a control system employing a central minicomputer. The single board computer, together with a small number of additional standard boards, is used to replace purpose-designed serializing and interfacing hardware. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan