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Solid-State Circuits, IEEE Journal of

Issue 5 • Date Oct. 1979

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Displaying Results 1 - 25 of 25
  • [Inside front cover - October 1979]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (October 1979)

    Page(s): 785
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    Freely Available from IEEE
  • Foreword: Special Issue on Semiconductor Memory and Logic

    Page(s): 786
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    Freely Available from IEEE
  • A 30-ps Josephson current injection logic (CIL)

    Page(s): 787 - 793
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    A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations. View full abstract»

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  • A compact efficient Schottky collector transistor switch

    Page(s): 801 - 806
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    A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage. View full abstract»

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  • (MI)/SUP 2/L: multiinput-multioutput integrated injection logic

    Page(s): 807 - 811
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    The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop. View full abstract»

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  • A versatile ECL multiplexer IC for the Gbit/s range

    Page(s): 812 - 817
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    A new approach to digital multiplexing for communication systems operating in the Gbit/s range is presented. With a single function, monolithically integrated in the established silicon bipolar process, many operations required by the communication system's multiplex equipment are achieved at data rates of up to 3 Gbits/s. The IC is a four-channel multiplexer designed to interface readily with ECL families. Demonstrations of the ICs performance include pseudorandom pattern generation by multiplexing ECL inputs up to 2 Gbits/s, demultiplexing into ECL registers at 1 Gbits/s, clock extraction in a 560 Mbit/s coaxial cable transmission system, and a modulo-n divider technique for timing generation using ECL feedback shift registers for frequencies up to 1.6 GHz. The demonstrations highlight the multiplexer's ability to effectively extend the system speed limit of commercially available ECL from a few hundred Mbits/s to the Gbit/s range. An eight-input multiplexer using three chips in a hybrid assembly is demonstrated multiplexing a static input pattern up to 2.8 Gbits/s. View full abstract»

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  • A 1500 gate, random logic, large-scale integrated (LSI) masterslice

    Page(s): 818 - 822
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    Describes the development for the bipolar gate array masterslice for custom designed logic. One chip is designed containing an array of standard logic gates which are then interconnected in a custom manner by using the various levels of metal on the chip. One such masterslice contains 1500 logic gates. The authors describe the physical organization of the chip, and the software package used to assist in simulating the logic, wiring the chip, and generating the patterns needed to test that specific logic function. The internal gate is described in detail, and a discussion of some of the design tradeoffs made is included. The peripheral level-shifting circuits used to interface with a T/SUP 2/L environment and an on-chip reference generating circuit are described. The testing philosophy used, and the package within which the chip is placed are discussed. The paper concludes with a description of the bipolar process used to manufacture the chip. View full abstract»

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  • A masterslice LSI for subnanosecond random logic

    Page(s): 829 - 832
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    Describes the design and implementation of a bipolar subnanosecond gate arrays with a complexity up to 700 gates. There are three different basic arrays with either 24 or 36 cells or 24 cells plus a 128 bit RAM. Each cell has the logic power of a small MSI. The masterslice is ECL compatible. View full abstract»

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  • A study in the use of PLA-based macros

    Page(s): 833 - 840
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    Describes a study in which a PLA-based macro design of a small processor is carried out in the same technology as the original `random' logic design of the same processor. The objectives of the study were to determine gains or losses in `technology utilization' when a PLA-based approach is used to replace the more conventional `random' logic approach. The results in this case are a design of equal performance and density, with only one-third the power dissipation of the original design. View full abstract»

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  • A pair of bipolar memory LSI chips for mainframe computers

    Page(s): 844 - 849
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    A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address access time of 6.7 ns and a typical power dissipation of 3.9 W. It is used in the translation lookaside buffer and the buffer address array of Hitachi's M200H computer to speed up dynamic address translation and buffer storage control. The other chip is a standard 1K bit RAM with a typical address access time of 5.5 ns and a typical power dissipation of 800 mW. It is used in the buffer storage. The primary fabrication process employs oxide isolation with double layer metallization, with minimum line width-plus-spacing of 8 /spl mu/m. View full abstract»

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  • An ECL 100K-compatible 1024x4 bit RAM with 15 ns access time

    Page(s): 850 - 854
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    An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time, 900 mW power dissipation, and a chip size of 18.3 mm/SUP 2/ has been developed for caches and control memories of high-performance computer systems. The 1K/spl times/4 organisation mode combines the lower cost per bit of a 4K-bit device with the higher memory-module design flexibility of a 1K word unit. The excellent speed performance together with the high packing density have been achieved by using an oxide isolation technology with oxide-walled emitters in conjunction with novel circuit techniques. View full abstract»

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  • A 65 mW 128K EB-ROM

    Page(s): 855 - 859
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    A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively. View full abstract»

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  • 16K CMOS/SOS asynchronous static RAM

    Page(s): 867 - 872
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    A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules. View full abstract»

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  • Approaches to high performance SITL

    Page(s): 873 - 875
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    In order to improve speed performance, the normally configured bipolar mode SIT (BSIT) is introduced to SITL with a new circuit configuration where output Schottky diodes are fabricated to ensure the decoupling between multiple outputs.. The performance of this Schottky SITL is evaluated in the ring oscillator having three fanouts for each state, where the propagation decay is obtained as 2.5 ns with a power dissipation of 100 /spl mu/W. View full abstract»

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  • Considerations for high-speed and analog-circuit-compatible I/sup 2/L and the analysis of Poly I/sup 2/L

    Page(s): 876 - 887
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    Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages. View full abstract»

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  • The effect of downward gain on the maximum toggle frequency of I/sup 2/L, linear compatible flip-flops

    Page(s): 896 - 898
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    Data are presented that show toggle rate versus minimum gate current for an I/SUP 2/L, linear compatible bipolar integrated circuit. The maximum toggle rate for a given gate current is dependent upon h/SUB FE/, verifying previous results using inverter chains. At relatively high gate currents, this dependency is seen to vary as approximately (h/SUB FE/)/SUP 1/2/. Deep emitter (super-gain) processing techniques were used to obtain toggle rates up to 12 MHz for conservative gate designs. View full abstract»

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  • [Back inside cover - October 1979]

    Page(s): b1
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    Freely Available from IEEE
  • Dynamic effects in Josephson devices operated as logic gates

    Page(s): 887 - 895
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    The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of ≥3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction. View full abstract»

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  • The punchthrough device as a passive exponential load in fast static bipolar RAM cells

    Page(s): 840 - 844
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    It is shown that the punchthrough device can be used as a passive exponential load in fast static bipolar RAM cells. The advantages are that the cell standby/read current ratio can be very large (> four decades), and that the cell area can be very small due to the fact that the punchthrough load is a vertical device. In this cell, a very small standby power dissipation(<0.1 μW) is combined with a short access time (<10 ns). A static noise margin calculation for the cell is included. The general standby/read switching behaviour of memory cells with exponential loads is explained. The cell sensitivity to α-particles is discussed. View full abstract»

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  • Experimental single flux quantum NDRO Josephson memory cell

    Page(s): 794 - 796
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    Single flux quantum nondestructive readout (NDRO) Josephson memory cells which store an energy of only ~6×10/SUP -20/ J have been successfully fabricated and operated for the first time. Margin enhancement due to quantization, and low operating currents render this cell an attractive basis for a <1 ns access-time Josephson cache memory designed with a 2.5 μm technology. View full abstract»

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  • The collector-coupled static RAM cell

    Page(s): 865 - 867
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    The collector-coupled static RAM cell uses a schottky collector transistor switch with merged vertical n-p-n load. The cell is constructed with two dual Schottky collector transistors and one merged dual collector n-p-n transistor. It has been fabricated in an infant oxide isolated bipolar technology and bistability has been demonstrated over four orders of magnitude in cell current (10 nA<I/SUB CELL/<100 μA). The approach taken here of stacking active load and switch elements provides static bit densities comparable to MOS memory and superior to other known bipolar approaches. View full abstract»

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  • New input/output designs for high speed static CMOS RAM

    Page(s): 823 - 828
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    New input and output schematics and optimum design for cell and array are proposed, and applied to a 256×4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 μm layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation. View full abstract»

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  • GaAs enhancement mode FET-tunnel diode ultra-fast low power inverter and memory cell

    Page(s): 797 - 800
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    A microtunnel diode load for a normally off enhancement mode gallium arsenide field effect transistor provides a compact inverter circuit of fast switching speed and low power consumption. Level shifting is not required, and direct coupling with multiple fan-out causes a comparatively small decrease in speed. The tunnel diode FET logic (TDFL) should be capable of operation at 2 GHz with a power-delay time product of 3.4 fJ for an output node capacitance of 50 fF. The negative characteristic of the tunnel diode combined with the FET provides a compact memory cell. However, advances in the state of the art for producing microtunnel diodes of precisely controlled peak current will be required before a viable TDFL can emerge. View full abstract»

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  • CMOS/SOS EAROM memory arrays

    Page(s): 860 - 864
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    A new low-voltage nonvolatile memory cell has been fabricated using standard CMOS/SOS processing. The cell can be programmed at 10 V, conducts 400 μA when programmed, and can be erased either electrically or with UV light. Using this cell, a family of memories have been built which dissipate only 50 μW at 5 V, retain data for 17.3 years at 125°C, and have a WRITE/ERASE endurance in excess of 300 cycles. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan