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Solid-State Circuits, IEEE Journal of

Issue 2 • Date April 1979

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Displaying Results 1 - 25 of 48
  • [Inside front cover - April 1979]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (April 1979)

    Page(s): 177 - 528
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    Freely Available from IEEE
  • Foreword (April 1979)

    Page(s): 178 - 179
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    Freely Available from IEEE
  • Guest Editors' Note (April 1979)

    Page(s): 180
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    Freely Available from IEEE
  • 1 /spl mu/m MOSFET VLSI technology. I. An overview

    Page(s): 240 - 246
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    Highlights of various aspects of the technology development are discussed briefly. These include device design, circuit design, hot-electron effects, processing technology, electron-beam lithography, metal silicide interconnections and radiation effects. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications

    Page(s): 247 - 255
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    For pt.I see ibid., vol.SC14, no.2, p.240 (1979). Micrometer-dimension n-channel silicon-gate MOSFETs optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fanout and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

    Page(s): 255 - 268
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    For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

    Page(s): 268 - 275
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    For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

    Page(s): 275 - 281
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    For pt. IV see ibid., vol.SC14, no.2, p.268 (1979). An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 /spl mu/m, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

    Page(s): 282 - 290
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    For pt.V see ibid., vol.SC14, no.2, p.275 (1979). The authors discuss the fabrication of 1 /spl mu/m minimum linewidth FET polysilicon-gate devices and circuits, with emphasis on vector-scan electron-beam technology and processing. Different types of 1 /spl mu/m MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. VII. Metal silicide interconnection technology - A future perspective

    Page(s): 291 - 293
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    For pt.VI see ibid., vol.SC14, no.2, p.282 (1979). A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi/SUB 2/ (polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions. View full abstract»

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  • 1 /spl mu/m MOSFET VLSI technology. VIII. Radiation effects

    Page(s): 294 - 301
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    For pt.VII see ibid., vol.SC14, no.2, p.291 (1979). The effect of electron-beam radiation on polysilicon-gate MOSFETs is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. View full abstract»

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  • A new polysilicon process for a bipolar device-PSA technology

    Page(s): 307 - 312
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    A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an ECL gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 /spl mu/m/SUP 2/ gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000 /spl mu/m/SUP 2/ gate area has been successfully developed. View full abstract»

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  • A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

    Page(s): 312 - 318
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    A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI. View full abstract»

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  • Scaling I/sup 2/L for VLSI

    Page(s): 318 - 327
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    Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted. View full abstract»

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  • An investigation of the intrinsic delay (speed limit) in MTL/I/sup 2/L

    Page(s): 327 - 337
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    Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. The injection model is used, into which new charge storage parameters are introduced. The majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. A device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4. View full abstract»

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  • A simple current model for short-channel IGFET and its application to circuit simulation

    Page(s): 358 - 367
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    The author describes a simple one-dimensional current model for an enhancement-insulated field-effect transistor (EIGFET), taking account of the carrier drift-velocity effect and short-channel effect. The model has been used for simulating various characteristics of an EIGFET of channel length of about 1 /spl mu/m and up, and in the simulation of the waveforms of a ring oscillator where each element transistor has a 1-/spl mu/m channel length. In either case, fairly good agreement was obtained between simulated results and measurements. View full abstract»

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  • Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis

    Page(s): 375 - 383
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    An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed. View full abstract»

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  • A 64 Kbit MOS dynamic random access memory

    Page(s): 482 - 485
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    A 65536 word/spl times/1 bit dynamic random access memory is developed using 4 /spl mu/m design rules, a 320-/spl Aring/ thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 Kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW. View full abstract»

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  • An electrically alterable nonvolatile memory cell using a floating-gate structure

    Page(s): 498 - 508
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    An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 /spl mu/m/SUP 2/, and using an advanced n-channel, polysilicon gate process. Cell programming occurs via hot-electron injection, exhibiting three distinct operating regimes. Erase, on the other hand, is based on field emission from floating gate to control gate. The magnitude of electrical erase is determined by applied bias, device parameters, and processing history, particularly the interlevel oxidation temperature. Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design. A 5-V, 16K high-speed EAROM has been developed which shows successful programming and erase behaviour at nominal voltages of 25 and 35 V, respectively. View full abstract»

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  • A 7000-gate microprocessor on SOS-PULCE

    Page(s): 510 - 517
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    An n-channel MOS LSI microprocessor integrating 20000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. View full abstract»

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  • Analog-binary CCD correlator: a VLSI signal processor

    Page(s): 518 - 525
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    Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code load logic, and TTL-to-MOS converters. Design of the floating-gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. Electron-beam lithography was used to produce photomasks with low defect density and tight dimensional tolerances over the array. View full abstract»

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  • [Back inside cover - April 1979]

    Page(s): b1
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    Freely Available from IEEE
  • VLSI limitations from drain-induced barrier lowering

    Page(s): 383 - 391
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    Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount. View full abstract»

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  • Impact of VLSI from communications viewpoint

    Page(s): 204 - 205
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    The author presents the future prospect for LSI utilization in communication systems, a short history of IC development at Nippon Laboratories, and an outline of the LSI project. The initial targets of the project and some results obtained in LSI design and fabrication, including progress in processing tools, are shown. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan