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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Aug. 1978

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Displaying Results 1 - 25 of 25
  • [Inside front cover - August 1978]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1978)

    Page(s): 417
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    Freely Available from IEEE
  • Foreword (August 1978)

    Page(s): 418
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    Freely Available from IEEE
  • A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers

    Page(s): 436 - 444
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    Data are obtained using a microelectronic van der Pauw resistor structure in conjunction with automated test, computing, and graphic display equipment. Computer-drawn vector displacement maps, equivalue contour maps, and histograms are used to display the data in a format which assists in the interpretation of sources of MSE. A six-parameter model which takes into account mask translation, rotation, and expansion is shown to fit successfully the data obtained from test wafers masked using conventional alignment equipment. A comparative evaluation of the performance of a group of aligners used for manufacturing integrated circuits is given, and an investigation of the consequences of masking silicon wafers which have been subjected to high-temperature processing is performed. View full abstract»

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  • A new buried-oxide isolation for high-speed high-density MOS integrated circuits

    Page(s): 468 - 471
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    The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices. View full abstract»

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  • An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

    Page(s): 472 - 478
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    An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed. View full abstract»

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  • A new high-voltage analog-compatible I/sup 2/L process

    Page(s): 479 - 483
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    A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V. View full abstract»

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  • I/sup 2/L with polysilicon diode contact

    Page(s): 483 - 489
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    A polysilicon diode is used instead of a Schottky diode in I/SUP 2/L/MTL to reduce the signal swing. The new method enables improvement of the power-delay product of a conventional I/SUP 2/L, which has heavily doped collectors, without detriment to process simplicity, while retaining high-packing density and compatibility with other bipolar circuits. Experiments demonstrate a factor of 2.5 to 3 improvement in propagation delay at a low-current level. However, high-current operation is restricted by decreased noise margin with increasing current level. View full abstract»

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  • Modelling and optimization of the oxide isolated substrate fed I/sup 2/L structure

    Page(s): 491 - 499
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    A large-signal model is derived for the substrate fed integrated injection logic (I/SUP 2/L) gate which is suitable for computer-aided circuit design and the optimization of the physical structure. Since the analysis extends the Ebers-Moll model it differs from the existing models in that the effects of high-level injection and injector debiasing are included. Furthermore, heavy doping effects are included in the calculation of currents and minority carrier storage. The analysis of the oxide isolated structure predicts circuit delays of less than 5 ns at 50 /spl mu/A. View full abstract»

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  • A low drift fully integrated MOSFET operational amplifier

    Page(s): 499 - 503
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    A fully integrated MOSFET amplifier with very low drift has been built using standard technology. Input offset voltages as low as 5 /spl mu/V and drift values of this offset voltage less than 0.05 /spl mu/V//spl deg/C are measured. View full abstract»

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  • An automatic C-V plotter and junction parameter measurements of MIS Schottky barrier diodes

    Page(s): 510 - 514
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    An automatic C-V plotter which employs phase-locked loop integrated circuits to sense the in-phase and quadrature-phase current signal passing through the diode under test is described. The output voltage at a moderately high frequency is directly proportional to the junction capacitance of the diode when the reference signal of the phase detector is in phase with the input signal. The junction resistance of the diode can be simultaneously determined by measuring the quadrature-phase signal. This instrument has successfully measured the C-V characteristics of Schottky barrier solar cells. View full abstract»

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  • A 12-18 GHz medium-power GaAs MESFET amplifier

    Page(s): 520 - 527
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    Two medium-power 12-18 GHz GaAs FET amplifiers, one single-ended and one balanced, have been developed. A minimum output power across the Ku-band of 200 mW with an associated gain of 4.0 dB was achieved with the balanced module. The transistor used in this study has gate dimensions of 300/spl times/1/spl mu/m. The technology, RF performance, and characterization of the transistor are discussed in detail, as are the design and performance of both single-ended and balanced amplifier modules. View full abstract»

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  • Comments on "Multiple diode constant current sources"

    Page(s): 528
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    Comment is made on the current temperature coefficient of a recently described multiple diode constant current circuit, (see S. Pookaiyaudom et al., ibid., vol.SC-12, no.5, p.587 (1977)). View full abstract»

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  • Application of the translinear principle in digital circuits

    Page(s): 528 - 530
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    The translinear principle, which is useful in the design of analog integrated circuits, can also be applied to the design of digital integrated circuits. As an example of this technique, a new nonsaturating bistable element is described, which operates according to the translinear principle and which is realizable with standard bipolar integrated circuit processes. The circuit can operate over a wide range of supply current from some milliamperes down to below 1 nA. View full abstract»

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  • [Back inside cover - August 1978]

    Page(s): b1
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    Freely Available from IEEE
  • Properties of Be-implanted planar GaAs p-n junctions

    Page(s): 426 - 429
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    The fabrication and characteristics of planar junctions in GaAs formed by Be ion implantation are discussed. The critical processing step is shown to be the use of a carefully deposited oxygen-free Si/SUB 3/N/SUB 4/ encapsulation during post-implantation annealing. Forward and reverse characteristics are presented for Be-implanted junctions formed by encapsulating with SiO/SUB 2/, Si/SUB x/O/SUB y/N/SUB z/, or Si/SUB 3/N/SUB 4/ layers prior to annealing at 900°C. Junctions which exhibit leakage current density of ~2×10/SUP -7/ A/cm/SUP 2/ at 80 V reverse bias and breakdown voltage >200 V have been fabricated using RF-plasma deposited Si/SUB 3/N/SUB 4/ layers as the encapsulant. View full abstract»

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  • JFET's fabricated in a standard IC process for bipolar transistors

    Page(s): 530 - 532
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    A new method for the fabrication of n- and p-channel JFETs in a standard IC process for bipolar transistors is presented. Using special layout techniques, which are based on well-known principles, JFETs of good performance are obtained, provided a tightly controlled photoresist process is available. View full abstract»

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  • Development ot ohmic contacts for GaAs devices using epitaxial Ge films

    Page(s): 430 - 435
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    Ohmic contacts to n-type GaAs have been developed using epitaxial Ge films on GaAs alloyed with Ni overlayers by solid-state diffusion at temperatures of 450°C-650°C. These contacts have applications to high reliability, high temperature microwave devices. Reflection electron diffraction of the Ge layers prior to deposition of the Ni overlayers reveals the presence of high quality single-crystalline films. Even after sintering, there is very little penetration of Ge into GaAs in the absence of Ni. With the presence of a Ni overlayer, significant interdiffusion between Ge and GaAs is revealed by Auger electron spectroscopic profiles. These results, together with the current-voltage characteristics of similar contacts prepared on p-type GaAs, indicate the presence of a Ge-doped n/SUP +/ layer at the Ni/Ge-GaAs interface. Ohmic contacts using epitaxial Ge films with Ta and Mo overlayers have also been investigated. View full abstract»

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  • Substrate voltage bounce in NMOS self-biased substrates

    Page(s): 515 - 519
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    The problem of substrate voltage bounce is discussed for NMOS LSI random logic designs which operate from self-biased substrates. Using chip capacitance and switching noise probability models, the impact of voltage bounce on threshold voltage variation (V/SUB T/-sigma) is illustrated and a comparison is made with designs operating from externally biased substrates. To achieve the potential performance improvement made possible through the use of substrate generators, off-chip capacitors are recommended to improve V/SUB T/-sigma control. View full abstract»

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  • Planar GaAs IC technology: Applications for digital LSI

    Page(s): 419 - 426
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    This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 μW/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated. View full abstract»

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  • Planar multilevel interconnection technology employing a polyimide

    Page(s): 462 - 467
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    A planar multilevel interconnection technology, called planar metallization with polymer (PMP), has been developed, which utilizes a polyimide known as PIQ (polyimide isoindroquinazoline-dione) as an interlevel dielectric. The PIQ is highly resistant to heat and is mechanically flexible. Its low impurity concentrations also make it very stable in semiconductors. The PMP processing techniques have been refined to the stage where ICs can be fabricated commercially. A PIQ film etchant forms fine via-holes up to 3×3 μm/SUP 2/, and chip size can be reduced by placing bonding pads on the active region of the device. Highly reliable linear and 256-bit bipolar memory ICs have been realized through this technology. View full abstract»

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  • CMOS pulse-code-modulation voice codec

    Page(s): 504 - 510
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    A standard CMOS technology has been employed in LSI realization of a pulse-code-modulation (PCM) encoder and decoder for per-channel applications in telephony. Innovations in the design of an operational amplifier, a comparator, and precision-ratioed capacitor arrays, all in standard CMOS, are reported. View full abstract»

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  • Inversion charge transistor (ICT) for better threshold control in small dimensions

    Page(s): 490 - 491
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    Data are presented to show that threshold voltage is less dependent on channel length for an inversion charge transistor than for a regular IGFET. Thus, for an acceptable threshold tolerance, an inversion charge transistor can be operated with a smaller channel length than an IGFET. View full abstract»

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  • Modelling and measurement of surface impurity profiles of laterally diffused regions

    Page(s): 455 - 461
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    Analytic solutions for two-dimensional diffused profiles are obtained for a drive-in in an inert ambient and in an oxidizing ambient. For both cases, the impurity profiles have the same lateral dependence. An experiment which extracts the surface impurity profile near a diffusion mask edge is described. Test structures for this purpose have been fabricated using a CMOS process. View full abstract»

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  • Effects of RF annealing on the excess charge centers in MIS dielectrics

    Page(s): 445 - 454
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    Excess fixed charge and surface states in various MIS structures have been successfully removed by the RF annealing technique. Important processing parameters that are pertinent to a successful anneal have been defined. A qualitative model is proposed to describe the annealing mechanisms, and to account for the experimental results. It is thought to be a cooperative effect involving the RF field, the plasma radiation, and the induced wafer temperature. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan