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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Aug. 1977

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  • [Inside front cover - August 1977]

    Publication Year: 1977 , Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1977)

    Publication Year: 1977 , Page(s): 333
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    Freely Available from IEEE
  • Foreword: Special Issue on Semiconductor Materials and Processing Technology

    Publication Year: 1977 , Page(s): 334
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    Freely Available from IEEE
  • A new multiplexed electrode-per-bit structure for a 64-kbit charge-coupled-device memory

    Publication Year: 1977 , Page(s): 335 - 343
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1178 KB)  

    An advanced form of the multiplexed electrode-per-bit (ME/B) structure is described for CCD memory applications. In the new structure, a merging serial register is combined with an ME/B array to make a practical and flexible CCD array. The resulting structure is called the merging ME/B (M/SUP 2/E/B). An n-channel two-level polysilicon-gate structure with ion-implanted barriers and offset CCD clocks lead to a simple rectangular layout, in addition to low power consumption. A 64-kbit CCD memory utilising the structure was designed and tested. The memory operates typically at 5-Mbits/s data rate, while a 512-bit test array is operated in less than 140-ns transfer execution time. View full abstract»

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  • C/sup 2/L: A new high-speed high-density bulk CMOS technology

    Publication Year: 1977 , Page(s): 344 - 349
    Cited by:  Papers (7)  |  Patents (3)
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    C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS). View full abstract»

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  • Effects of the diffused impurity profile on the DC characteristics of VMOS and DMOS devices

    Publication Year: 1977 , Page(s): 356 - 362
    Cited by:  Papers (7)  |  Patents (2)
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    Double-diffused MOS (DMOS) and V-groove MOS (VMOS) transistors have been simultaneously fabricated in order to investigate the effects of impurity profiles on device performance. Processing parameters are varied to achieve a range of channel lengths and peak channel dopings. The resulting impurity profiles are measured by the two point probe spreading resistance method. Properties of the lateral DMOS impurity profile are inferred from a comparison of the electrical characteristics of the VMOS and DMOS devices. It is found that conventional models inadequately simulate the output conductance of the devices in saturation. An expression for channel length modulation is derived from a one-dimensional solution of Poisson's equation in the region surrounding the channel-drain junction. When measured impurity profile data are incorporated into the new channel length modulation model, the output conductance of the devices is accurately simulated for channel lengths ranging from 0.6 to 2.0 /spl mu/m. View full abstract»

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  • Poly I/sup 2/L-a high-speed linear-compatible structure

    Publication Year: 1977 , Page(s): 367 - 375
    Cited by:  Papers (18)  |  Patents (7)
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    Poly I/SUP 2/L a new bipolar process technology, is presented featuring 5 ns minimum propagation delay, 24 MHz flip-flop operation (using 10 /spl mu/ minimum feature size), and 15-30 V isolated and unconstrained linear circuit transistors on 5 /spl Omega/.cm epitaxy. Standard linear integrated circuit process complexity is increased by only one mask without extra diffusions. View full abstract»

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  • A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

    Publication Year: 1977 , Page(s): 376 - 382
    Cited by:  Papers (4)
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    A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology. View full abstract»

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  • A quad JFET wide-band operational-amplifier integrated circuit featuring temperature-compensated bandwidth

    Publication Year: 1977 , Page(s): 382 - 388
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (723 KB)  

    Previous quad operational-amplifier integrated circuits were not always suited to active-filter applications because of limited small-signal bandwidths, bandwidths changing over temperature, limited slew rates, and low-power bandwidth. To more optimally meet these requirements a new circuit has been designed using ion-implanted JFET devices. As a result of circuit simplicity, four independent, internally compensated, 10-MHz amplifiers have been fabricated on a single 84/spl times/94-mil die. View full abstract»

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  • Wide-band active variable tuning circuits

    Publication Year: 1977 , Page(s): 389 - 394
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    Active variable tuning circuits having a constant bandwidth or a constant Q value are described. Their resonant frequency can be varied continuously over a considerable range maintaining high performance. A generalised immittance convertor (GIC) is used as variable reactance and a new compensation technique using negative capacitance is proposed. The validity of the theory is confirmed by experiments employing ganged variable resistances as variable elements in the tuning circuits. The variable resistances are replaced by periodically switched resistances to obtain circuits which can change their resonance frequency linearly with voltage and are suited for integrated circuits. As a practical application, low frequency spectrum analysers are described. View full abstract»

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  • Analysis of forward-bias p-i-n-diode inductive driving

    Publication Year: 1977 , Page(s): 394 - 402
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    Published literature on p-i-n-diode driving circuits for phase-shifter applications is rather rare and contains descriptions or analyses of driving circuits with at least two high-power transistors as output devices. This paper presents design criteria for a high-power p-i-n-diode inductive driver, as well as analytical and experimental results for the forward-bias transition of p-i-n-diodes. Expressions are developed that enable one to predict the switching waveforms and the p-i-n-diode storage charge with very good accuracy. In developing these expressions the effects of circuit parameters and the parasitic capacitance due to the p-i-n-diode packaging and phase-shifter mounting have been taken into account. View full abstract»

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  • An integrated JK flip-flop circuit

    Publication Year: 1977 , Page(s): 403 - 406
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained. View full abstract»

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  • Dual depletion CMOS (D/sup 2/CMOS) static memory cell

    Publication Year: 1977 , Page(s): 424 - 426
    Cited by:  Papers (6)
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    A new type of static memory cell-dual depletion CMOS (D/SUP 2/MOS)-has been designed and fabricated using SOS wafers by the conventional CMOS/SOS technology. In contrast to the conventional CMOS static memory cell, which comprises six transistors, the new cell consists merely of four transistors and one data-line so that the cell area can be significantly reduced. View full abstract»

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  • A bandpass filter using the operational amplifier pole

    Publication Year: 1977 , Page(s): 429 - 430
    Cited by:  Papers (4)
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    The operational amplifier rolloff characteristics and a single capacitor are used for obtaining an inverting bandpass function. The filter performance depends on the gain-bandwidth product of the operational amplifier. Experimental results are included. The amplifier rolloff characteristics can be utilised in deriving transfer functions. The resulting filters have an extended frequency range of operation and a reduced number of external capacitors. View full abstract»

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  • An integrated illumination-to-frequency converter

    Publication Year: 1977 , Page(s): 430 - 433
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    A simple integrated illumination-to-frequency converter has been fabricated following the field-effect modified transistor (FEMT) as suggested by Nordstrom and Meindl (1972). The authors have made a careful analysis of the performance of the device and have found that no external photodiode is needed for the device to operate properly. An external capacitor, connected across the external base to collector junction can significantly extend the range of operation of the device as a light detector. View full abstract»

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  • A standardized approach for the reduction of LSI design time and automatic rules checking

    Publication Year: 1977 , Page(s): 433 - 436
    Cited by:  Papers (2)
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    A design method, based upon the use of standardized basic elements is proposed. A symbolic layout technique, associated with network recognition programs, enables a fast and secure design. That method has been applied to CMOS technology and practical results demonstrate its efficiency. View full abstract»

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  • Correction to "A Circuit Technique for Broadbanding the Electronic Tuning Range of Gunn Oscillators"

    Publication Year: 1977 , Page(s): 436
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    First Page of the Article
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  • [Back inside cover - August 1977]

    Publication Year: 1977 , Page(s): b1
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    Freely Available from IEEE
  • Inductor-less, capacitor-less state-variable electrothermal filters

    Publication Year: 1977 , Page(s): 416 - 424
    Cited by:  Papers (3)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    Electrothermal circuits (ETC) exploit interactions between thermal and electronic properties of devices in an integrated circuit to perform useful electronic functions. An ETC integrator is described which can be used as a building block for state-variable filters. Circuits are given which perform the coefficient-setting function for such filters. Measured data are given for low-pass, high-pass, bandpass, and notch state-variable ETC filters; these filters use only transistors and resistors. For the chip size used, the maximum frequency of the filters is of the order of 200 Hz; an order of magnitude increase is possible with reduced chip size. Methods are described for making filter performance independent of ambient temperature. View full abstract»

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  • Submicron patterning of surfaces

    Publication Year: 1977 , Page(s): 363 - 367
    Cited by:  Papers (6)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A new process for providing submicron patterning of surfaces is presented. This processing technique, which the authors call the Iso-E process, is capable of producing submicron openings to the surface of materials using conventional photolithographic techniques and processing common to the semiconductor industry. This process can be used equally well with X-ray or electron-beam lithography to provide minimum geometry openings at minimum geometry spacings. View full abstract»

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  • Monolithic crosspoint arrays for private automatic branch exchanges (PABX)

    Publication Year: 1977 , Page(s): 407 - 415
    Cited by:  Papers (3)
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    This paper presents economical technical solutions for monolithic integrated semiconductor crosspoint arrays for PABXs. It starts with the description of IGFET switches and I/SUP 2/L-bipolar transistor switches. Then, realised symmetrical crosspoint arrays with these switches are treated, beginning with the integration level and the logic concept. Monolithic integrated crosspoint arrays with 5×2 balanced crosspoints in PMOS technology, NMOS Si-gate technology, and I/SUP 2/L technology are described in detail. Measurements for PMOS and I/SUP 2/L arrays show that for a one-stage PABX all transmission requirements at least are fulfilled. With an I/SUP 2/L-bipolar transistor array even switching networks with three stages are possible, since ON-resistances of these switches are especially low. View full abstract»

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  • Precise integrator for linear delta modulator

    Publication Year: 1977 , Page(s): 426 - 427
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    A constant slope integrator for single integration linear delta modulation (LDM) will be described. The circuit essentially is a bootstrapped sweep generator, capable of generating positive and negative sweep voltages. It uses one transistor, four diodes, and two Zener diodes. The step size can be easily changed by changing the base resistance or charging capacitance. The circuit is versatile and may be used effectively in other waveform generators. The circuit is integrable. View full abstract»

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  • The current dependency of the output conductance of voltage-driven bipolar transistors

    Publication Year: 1977 , Page(s): 428 - 429
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    The current dependency of the output conductance of voltage-driven bipolar junction transistors (BJTs) is discussed. It is shown that by combining the established theories about basewidth modulation and thermal feedback the output admittance of voltage-driven BJTs can be accurately predicted over a large range of current levels. The current dependency of the output admittance of some basic IC configurations is discussed in detail. View full abstract»

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  • Correlation of fabrication process and electrical device parameter variations

    Publication Year: 1977 , Page(s): 349 - 355
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A program for modelling IC fabrication processes is described. Simulated and measured impurity profiles are shown for a bipolar transistor technology. These profiles are used to study the sensitivity of electrical device parameters to process variations. A comparison of simulated device performance using process models gives parameters which bracket measured results for 35 die across a wafer. A statistical model is given which relates twelve parameters to the base transport current. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan