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Solid-State Circuits, IEEE Journal of

Issue 3 • Date June 1977

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Displaying Results 1 - 25 of 32
  • [Inside front cover - June 1977]

    Publication Year: 1977 , Page(s): f2
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    Freely Available from IEEE
  • Table of contents (June 1977)

    Publication Year: 1977 , Page(s): 213
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  • Introduction from the Second European Solid-State Circuits Conference Chairman

    Publication Year: 1977 , Page(s): 214
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    Freely Available from IEEE
  • Foreword (June 1977)

    Publication Year: 1977 , Page(s): 215 - 216
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    Freely Available from IEEE
  • Editor's Note (June 1977)

    Publication Year: 1977 , Page(s): 216
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  • A low input capacitance voltage follower in a compatible silicon-gate MOS-bipolar technology

    Publication Year: 1977 , Page(s): 217 - 222
    Cited by:  Papers (4)  |  Patents (4)
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    Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p noise from 1 Hz to 100 kHz. Offset drift is less than 30 /spl mu/V//spl deg/C. The circuit is based on a new very high-gain differential stage which allows full bootstrapping of all its input capacitances. The circuit measures only 0.9 mm/SUP 2/ and is mounted in a 4-pin TO-18 package. The circuit can successfully be used for charge measurements, and especially for wide-band measurements from very high impedance sources (>10 M/spl Omega/) as occurring in bioelectronics, biochemistry, etc. View full abstract»

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  • A fast sample and hold charge-sensing circuit for photodiode arrays

    Publication Year: 1977 , Page(s): 232 - 237
    Cited by:  Papers (11)  |  Patents (7)
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    An on-chip charge-sensing circuit with a feedback loop has been designed for improving the charge-transfer speed in photodiode arrays. Its large output voltage swing combined with improved speed performances, makes this circuit well-suited for OCR applications, especially low-cost data capture devices. Sample and hold operation can easily be performed without increasing the Si real estate, making parallel output feasible with frame rates of 3 kHz for arrays with 500 pixels. Experimental arrays were built in standard p-channel aluminum-gate technology. View full abstract»

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  • The TDA1077 - An I/sup 2/L circuit for two-tone telephone dialing

    Publication Year: 1977 , Page(s): 238 - 242
    Cited by:  Papers (5)  |  Patents (1)
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    The circuit-design aspects of an integrated circuit to perform two-tone telephone dialing are described. The circuit is believed to be unique in that it combines both the crystal-controlled frequency synthesizer and the output amplifier on the same chip. Moreover, no external power supplies are required; the circuit is powered by the telephone-line current. Designed to require a minimum number of external components, the LSI chip provides an economical and accurate two-tone dialing unit. A typical application circuit for existing telephone apparatus is shown and aspects of future development are discussed. View full abstract»

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  • A new circuit configuration for a single-transistor cell using Al-gate technology with reduced dimensions

    Publication Year: 1977 , Page(s): 253 - 257
    Cited by:  Patents (2)
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    A single-transistor memory cell in Al-gate technology with 2.5 /spl mu/m line width with a new circuit configuration is introduced. In this cell, the ground line of one cell and the word line of the cell opposite the bit line share the same line. This circuit configuration leads to memory cells having a bit density of 5720 bit/mm/SUP 2/ even though it uses a single layer metallization. The voltage conditions in this cell differ from those in conventional storage cells, but do not reduce the operation range of the new cell. As design and circuit studies have shown, a 32 kbit memory can be realized on a chip area of about 15.4 mm/SUP 2/, having an access time of 200 ns and a power dissipation of 500 mW. View full abstract»

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  • A theoretical and experimental study of DMOS enhancement/depletion logic

    Publication Year: 1977 , Page(s): 264 - 270
    Cited by:  Papers (2)  |  Patents (1)
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    Enhancement/depletion (E/D) logic is an attractive application of the double-diffused MOS (DMOS) technology, since no extra diffusions or ion implantations are required. Design rules are studied taking into account several criteria such as space-saving and optimum noise immunity. It is evidenced that some particular features of the DMOS driver, such as the fact that short-channel characteristics are obtained from a full-size device, deeply modifies the relations existing between the electrical characteristics of a gate and its `real estate'. Results are compared to conventional E/D logic. Two specific design regions are pointed out: low power and high speed. The first one normally results from the standard DMOS technology, making use of a <111>, /spl pi/-substrate. The high-speed option requests a supplementary ion implantation for the load device. Technology is discussed. A simple silicon-gate DMOS process is presented. Its main feature is to be almost identical to a standard n-channel silicon-gate technology, except for a supplementary p-diffusion. Emphasis is given to the threshold voltage control problem. A new solution yielding an improved control is presented. The method is based on the use of doped silox as p-diffusion source, combined with ion implantation for the n/SUP +/ regions. View full abstract»

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  • Schottky collector I/sup 2/L

    Publication Year: 1977 , Page(s): 270 - 275
    Cited by:  Papers (5)  |  Patents (1)
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    A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described. View full abstract»

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  • Transconductance cancellation for operational amplifiers

    Publication Year: 1977 , Page(s): 310 - 311
    Cited by:  Papers (25)  |  Patents (1)
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    A low-cost internally compensated integrated-circuit operational amplifier occupying a small die area can be fabricated if the compensation capacitor value is low. This objective is attained when the amplifier-input-stage transconductance is reduced to a minimum provided the frequency response remains unchanged. A new technique, transconductance cancellation, meets the objective without extra devices or components. View full abstract»

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  • An accurate voltage-controlled negative resistance circuit

    Publication Year: 1977 , Page(s): 311 - 313
    Cited by:  Papers (2)
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    A novel voltage-controlled negative resistance circuit incorporating n-p-n current mirrors is presented. Fully compatible with silicon IC technology, the circuit provides linear negative resistance characteristics that can be set precisely with external resistors. Experimental results are presented for the basic circuit as well as some of its variants. View full abstract»

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  • A single-ended current gain cell with AGC, low offset voltage, and large dynamic range

    Publication Year: 1977 , Page(s): 322 - 323
    Cited by:  Papers (1)
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    A circuit using bipolar transistors is described; experimental results show good accuracy and linearity for current gains up to 100. Measured dynamic range is /spl plusmn/80 percent of the bias current. View full abstract»

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  • A serial-parallel multiplier using the NENDEP technology

    Publication Year: 1977 , Page(s): 323 - 325
    Cited by:  Papers (2)  |  Patents (1)
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    A 12-bit serial-parallel multiplier has been integrated in the NENDEP technology. The features of a logic circuit using dynamic two-phase ratioed logic, combined with depletion load devices, are described. The basic cell structure of the multiplier, which accepts both positive and negative numbers represented in the two's complement code, is given. Next the performance of the 12-bit multiplier is reported. The circuit operates at a frequency of 5 MHz with a 5-V supply and 0- to 12-V clock signals. Inputs and output are directly TTL-compatible. At higher voltages clock rates up to 7 MHz are allowed. View full abstract»

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  • Comments on "A low-pass biquad derived filter realization"

    Publication Year: 1977 , Page(s): 329 - 330
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    In the above paper, Brodie (see ibid., vol.SC-11, p.552-5, 1976) presents a biquad low-pass filter which requires only two operational amplifiers. The use of current differencing amplifiers for reduced operational amplifier count implementation of the biquad filter has been around for some time. However, Brodie does not mention that the low-pass form is not the only filter that can be achieved. If one allows one additional resistor for biasing, a true bandpass output is available. View full abstract»

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  • [Back inside cover - June 1977]

    Publication Year: 1977 , Page(s): b1
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    Freely Available from IEEE
  • Microwave characterization of GaAs MESFET and the verification of device model

    Publication Year: 1977 , Page(s): 325 - 329
    Cited by:  Papers (3)
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    The elements in the small-signal equivalent circuit model of a microwave GaAs MESFET have been related to the device parameters (i.e., device structure, semiconductor properties, and operating point) by device theories. This equivalent circuit is experimentally verified by small-signal 3-GHz microwave measurements at room and liquid-nitrogen temperatures. The method used for determining the values of equivalent circuit parameters is briefly described. View full abstract»

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  • Design of a high-gain FET amplifier operating at 4.4-5.0 GHz

    Publication Year: 1977 , Page(s): 285 - 290
    Cited by:  Papers (1)
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    Described here is the design and the electrical performance of a MESFET amplifier featuring an output power of 1 W with a gain of 34 dB over the frequency range from 4.4 to 5.0 GHz. The key elements that allowed the achievement of this performance were: high-gain power MESFET's, a circuit design technique based on power characterization of the MESFET's, and a low-parasitics integrated microstrip construction. The amplifier is intended to replace a medium power TWT in a telecommunication system. When compared with a typical 1-W TWT this solid-state amplifier not only requires a much simpler power supply, is lighter and has perhaps higher reliability, but also has some better electrical performances; this should result in better system performance. View full abstract»

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  • CMOS analog integrated circuits based on weak inversion operations

    Publication Year: 1977 , Page(s): 224 - 231
    Cited by:  Papers (292)  |  Patents (94)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 μW at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits. View full abstract»

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  • Laser testing of integrated circuits

    Publication Year: 1977 , Page(s): 247 - 252
    Cited by:  Papers (2)  |  Patents (3)
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    Comprehensive testing is one of the major impediments to the production of cheap LSI. This problem is caused by the small number of circuit nodes which are directly accessible and the time required for exhaustive testing. A technique is presented in which data are injected directly into the internal circuitry of an integrated circuit by a finely focused laser beam, at rates over 1 MHz, using an electrooptic modulator. A laser power of below 15 μW is needed for MOS circuitry, but larger powers are required for other logic families. In addition to the provision of an input to key nodes, two important semiconductor parameters can be measured by using the laser probe. Large savings in the time taken and ease of both fault detection and diagnosis are envisaged by the use of this test method (which involves little or no modifications to the circuit design of layout) when used in conjunction with conventional test equipment. View full abstract»

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  • Circuit implications of the metal-gate polysilicon source-and-drain MOST process

    Publication Year: 1977 , Page(s): 258 - 263
    Cited by:  Patents (1)
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    The use of polysilicon layers as a diffusion source opens the way to a number of device innovations. One of these is the metal-gate `polysilicon source-and-drain' (PSD) MOST. Its main feature is a shrinkage in device size caused by the `automatic' (i.e., without any explicit contact window) connection between diffused regions and a polysilicon interconnection level. The advantages of this new process are elucidated in a comparison between PSD-MOST circuits and the standard `polysilicon self-aligned gate' (PSAG)-MOST circuits. Technological details have a mixed effect on device-circuit characteristics. By structuring the comparison into a device, a cell, and a circuit level, specific effects can be isolated and subsequently pointed out. It is shown, that PSD circuits potentially lead to a 33 percent higher packing density at a 25 percent higher switching speed, compared to standard PSAG circuits. Reliability has also been improved as the active area consumption is reduced by 50 percent together with a 75 percent decrease in the number of contact windows. View full abstract»

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  • TNPT-an efficient method to simulate forced nonlinear RF networks in time domain

    Publication Year: 1977 , Page(s): 243 - 246
    Cited by:  Papers (2)
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    A new method to simulate forced nonlinear RF networks in time domain is introduced. This method is a generalization of the well-known steady-state algorithm of Trick and Aprille (1972). The proposed method allows one to calculate all time solutions until steady-state is reached similar to transient simulation (TR). It compares with steady-state like TR simulation with DC, and can therefore be considered to be a transient simulation of nonlinear periodic transients (TNPT). View full abstract»

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  • Linear signal transmission with optocouplers

    Publication Year: 1977 , Page(s): 298 - 302
    Cited by:  Papers (5)
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    Until now, optocouplers have not been considered very suitable for linear, isolating circuits, owing to their nonlinearity in the current transfer ratio. In this paper, a circuit for linear signal transmission consisting of a pair of optocouplers in a feedback arrangement is analyzed. The nonlinearity of the optocouplers is practically eliminated by using coupler pairs with good tracking in their transfer function. This paper analyzes the distortion and gain of such a circuit as a function of linearity tracking, modulation index, and LED-DC-bias level. Measurements reported in this paper show that with a linearity tracking of only 10 percent, stringent distortion requirements such as for analog signal transmission in telephony can be fulfilled. The circuit achieves a distortion of 0.5 percent based on a 10 percent linearity tracking at a modulation index of 0.2 and the temperature stability of the gain is -0.09 percent/°C. View full abstract»

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  • Resistance-CMOS circuits

    Publication Year: 1977 , Page(s): 283 - 285
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    By combining dynamic CMOS circuits with a few resistive components, very simple sequential logic circuits with static behavior are obtained (e.g., frequency dividers, flip-flops, decoders). Using silicon gate technology and reverse-biased polysilicon diodes for the resistive elements, the area is nearly half that required for corresponding standard CMOS circuits. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan