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IEEE Journal of Solid-State Circuits

Issue 2 • Date April 1977

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Displaying Results 1 - 25 of 26
  • [Back inside cover - April 1977]

    Publication Year: 1977, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (April 1977)

    Publication Year: 1977, Page(s): 89
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    Freely Available from IEEE
  • Editor's Notice (April 1977)

    Publication Year: 1977, Page(s): 90
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    Freely Available from IEEE
  • Foreword: Special Issue on Integrated Injection Logic

    Publication Year: 1977, Page(s):91 - 92
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    Freely Available from IEEE
  • Second generation I/sup 2/L/MTL: a 20 ns process/structure

    Publication Year: 1977, Page(s):93 - 101
    Cited by:  Papers (34)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1551 KB)

    A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following ... View full abstract»

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  • I/sup 2/L with a self-aligned double-diffused injector

    Publication Year: 1977, Page(s):109 - 114
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1051 KB)

    Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another fea... View full abstract»

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  • A new high speed I/sup 2/L structure

    Publication Year: 1977, Page(s):114 - 118
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (802 KB)

    A new improved I/SUP 2/L structure is discussed which has been shown to operate at high speeds with large fan-out capabilities while retaining low power operation. The new `up-diffused' structure is fabricated in such a fashion that Schottky diodes can be readily incorporated. With the addition of Schottky clamps between the collector and base of the n-p-n switching transistor, gate delays as low ... View full abstract»

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  • The Schottky I/sup 2/L technology and its application in a 24x9 sequential access memory

    Publication Year: 1977, Page(s):119 - 123
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (879 KB)

    The Schottky I/SUP 2/L device and a two-level metal scheme have been used to fabricate a 24/spl times/9 sequential access memory. The T/SUP 2/L compatible chip has 1287 Schottky I/SUP 2/L gates, operates at 60 mA, and requires an area of 13200 mil/SUP 2/. Details of the Schottky I/SUP 2/L technology and its application in a 24/spl times/9 sequential memory are discussed. View full abstract»

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  • Schottky I/sup 2/L (substrate fed logic) - An optimum form of I/sup 2/L

    Publication Year: 1977, Page(s):123 - 127
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (923 KB)

    A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applie... View full abstract»

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  • Schottky I/sup 2/L (substrate fed logic) - An analysis of the implications of the vertical injector structure and Schottky collection

    Publication Year: 1977, Page(s):128 - 135
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1038 KB)

    The DC behavior of a Schottky I/SUP 2/L gate is analysed by using the Ebers-Moll equations, modified to include Schottky diodes. The usual definition of I/SUP 2/L common emitter current gain is replaced by a new definition which is more suitable for the vertical injector structure of Schottky I/SUP 2/L. The analysis is general and can be applied to any multijunction structure containing Schottky d... View full abstract»

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  • Polycrystalline silicon as a diffusion source and interconnect layer in I/sup 2/L realizations

    Publication Year: 1977, Page(s):135 - 138
    Cited by:  Papers (7)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB)

    Boron-doped polycrystalline silicon is applied as a diffusion source for the p-type regions of I/SUP 2/L devices. The polysilicon also serves as a conductive level which requires no contact windows in the p-type regions. Compared to conventional processing a higher fan-out, size reduction, and a greater layout flexibility are reported. View full abstract»

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  • I/sup 2/L timing circuit for the 1 ms-10 s range

    Publication Year: 1977, Page(s):139 - 143
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (791 KB)

    An I/SUP 2/L timing circuit without external components is presented, which makes use of some specific I/SUP 2/L properties-operation at low power levels, light sensitivity, variable delay, and long maximum delay times. The circuit comprises 45 gates on a chip area of 0.3 mm/SUP 2/. It produces pulses from below 1 ms to more than 10 s which are inversely proportional to a single supply current. Fo... View full abstract»

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  • Base current of I/sup 2/L transistors

    Publication Year: 1977, Page(s):143 - 150
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1362 KB)

    For the I/SUP 2/L n-p-n transistor, a method is presented which allows the base current to be split into various components. This has been achieved by comparing, at a fixed emitter-base voltage, the base current of I/SUP 2/L devices, different in geometry. Several precautions against parasitic effects are described. The measurements have been carried out in the emitter-base voltage range of 540-65... View full abstract»

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  • Modeling device and layout effects of performance driven I/sup 2/L

    Publication Year: 1977, Page(s):155 - 162
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1231 KB)

    The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the speed-power product curve. This paper considers these three factors with the aid of a device model, ci... View full abstract»

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  • Modeling the dynamic behavior of I/sup 2/L

    Publication Year: 1977, Page(s):163 - 170
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1212 KB)

    The validity of the charge control approach is checked for the normal (upward) operation of an I/SUP 2/L gate, leading to the conclusion that deviations are mainly due to the distributed nature of the base resistance. An alternative method is presented to determine the relevant device parameters, starting from experimental data. An equivalent model, incorporating the distributed base resistance, i... View full abstract»

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  • A stored charge model for estimating I/sup 2/L gate delay

    Publication Year: 1977, Page(s):171 - 176
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    Calculated results with this model compare favorably to those obtained experimentally. This model not only provides physical insight into I/SUP 2/L device operation, but serves as a useful tool for device and process design optimization. View full abstract»

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  • Dynamic behavior of active charge in I/sup 2/L transistors calculated with lumped transistor models

    Publication Year: 1977, Page(s):176 - 184
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1436 KB)

    In this paper, a base for further detailed I/SUP 2/L lumped modeling work is given. The lumped model is used because of its close contact with internal physical processes. Transmission line effects can be included, using multilump models. Excess minority carrier plots, which can be derived from internal node voltages, visualize very clearly the behavior of the active charge. As an example, a trans... View full abstract»

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  • Role of the external n-p-n base region on the switching speed of integrated injection logic (I/sup 2/L)

    Publication Year: 1977, Page(s):185 - 191
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1077 KB)

    Two-dimensional simulation and charge control principles have been applied to reveal the factors which determine the minimum delay of an integrated injection logic (I/SUP 2/L) gate, and experimental verifications are carried out. Using a numerical analysis this paper shows that important factors in improving the speed of an I/SUP 2/L gate are reducing the amount of minority charge stored in the ex... View full abstract»

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  • An analytic model for the design and optimization of ion-implanted I/sup 2/L devices

    Publication Year: 1977, Page(s):191 - 198
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1166 KB)

    A set of simple analytic equations have been derived that model the transient characteristics of an I/SUP 2/L gate fabricated with ion implantation. The model equations are cast in terms of easily measured or calculated device parameters and are applicable at all current levels. Separate models for regions dominated by depletion and diffusion capacitance, respectively, are unnecessary. The model h... View full abstract»

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  • Computer-aided design of large-scale integrated I/sup 2/L logic circuits

    Publication Year: 1977, Page(s):199 - 204
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1059 KB)

    Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, c... View full abstract»

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  • Evaluation of electron injection current density in p-layers for injection modeling of I/sup 2/L

    Publication Year: 1977, Page(s):205 - 206
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Proportionality between electron injection current density and sheet resistance of p-layers having a sink boundary has been found over a two orders of magnitude range of sheet resistance. This facilitates prediction of electron injection parameters for injection modeling and process control of I/SUP 2/L/MTL. View full abstract»

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  • I/sup 2/L current gain design

    Publication Year: 1977, Page(s):206 - 281
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB)

    A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell. View full abstract»

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  • I/sup 2/L DC functional requirements

    Publication Year: 1977, Page(s):208 - 210
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (477 KB)

    Factors controlling the DC operational limits of integrated injection logic (I/SUP 2/L) imposed by the interaction between the inverse n-p-n switching transistors and the lateral p-n-p transistor formed with the injector are discussed. The operational limit is shown to be a function only of structural and doping level parameters. An upper limit on epitaxial resistivity is shown to result. View full abstract»

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  • Stacked I/sup 2/L circuit

    Publication Year: 1977, Page(s):210 - 212
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (387 KB)

    A new I/SUP 2/L circuit configuration is presented which cuts down the effective power dissipation of conventional I/SUP 2/L circuits to one third or even less. The basic idea of the new circuit concept is stacking the multiple blocks of I/SUP 2/L circuit layers and operating them in series connection. View full abstract»

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  • Some considerations on high-speed injection logic

    Publication Year: 1977, Page(s):150 - 154
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    After a brief review of the factors that limit the switching speed of standard I/SUP 2/L, the propagation delay time of some special high-speed I/SUP 2/L gates is computed. For a gate realized in oxide-isolated, shallow epitaxial layers, the delay time is directly dependent on the injector base width. Generally, the n-p-n switching transistor hardly contributes to the time delay. For a modified I/... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com