By Topic

Solid-State Circuits, IEEE Journal of

Issue 1 • Date Feb. 1977

Filter Results

Displaying Results 1 - 20 of 20
  • [Inside front cover - Febuary 1977]

    Page(s): f2
    Save to Project icon | Request Permissions | PDF file iconPDF (89 KB)  
    Freely Available from IEEE
  • Table of contents (February 1977)

    Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (49 KB)  
    Freely Available from IEEE
  • Editor's Note (February 1977)

    Page(s): 2
    Save to Project icon | Request Permissions | PDF file iconPDF (37 KB)  
    Freely Available from IEEE
  • A circuit technique for broadbanding the electronic tuning range of Gunn oscillators

    Page(s): 21 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    A circuit technique is described whereby the electronic tuning range obtained by varactor tuning solid-state oscillators, such as Gunn oscillators, can be improved. The principle of the technique has been demonstrated by doubling the tuning range obtained from a coaxial X-band Gunn oscillator using distributed circuit elements. An analytical expression for the improved tuning range is presented and predictions for the improvement in an existing microstrip X-band oscillator using chip devices given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simple but efficient analog computer for simulation of high-speed integrated circuits

    Page(s): 51 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (958 KB)  

    An analog computer is described which performs transient simulation of nonsaturated transistor circuits with little expense of time. The computer contains models of bipolar transistors and Schottky-barrier diodes as well as variable capacitors and resistors, all realized in plug-in technique. The parameters of the semiconductor devices are directly and continuously adjustable. Therefore, no special knowledge is required to operate the computer. For the display, a dual-trace oscilloscope with low bandwidth is sufficient because the analog time range lies above 0.1 ms. Compared with the digital computer simulation, this analog method has the advantages of lower costs and less simulation time, the latter allowing fast interaction between designer and computer. The good accuracy of the described simulation method is demonstrated by comparing the simulated and the directly measured transient response of an integrated subnanosecond E/SUP 2/CL gate. Also it is shown how the delay time of this gate depends on the transistor parameters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Monolithic nullor-a universal active network element

    Page(s): 59 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (807 KB)  

    The design of a monolithic integrated nullor is described. It is a universal active element with floating input and output ports and with large internal gain. The element consists of a differential input stage, a symmetrical level shift stage, and a differential output stage. In the latter stage the collectors of a long-tailed transistor pair function as a pair of connected vessels for the output currents at high common-mode output impedance. This gives the output port its floating character. The element is capable of conveying a potential from one input terminal to the other input terminal and a current from one input terminal to the other output terminal at an accurate unity gain. The total inaccuracy of these operations is in the order of 2/spl times/10/SUP 4/ at signal voltage levels of 1 V and 1 mA. The element has a bandwidth of 25 MHz and can handle maximum signal values of 10 V and 1 mA. The availability of such universal active elements makes it possible to minimize the number of active elements and passive precision elements in implementation of analog system functions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author's Reply

    Page(s): 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (126 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back inside cover - February 1977]

    Page(s): b1
    Save to Project icon | Request Permissions | PDF file iconPDF (95 KB)  
    Freely Available from IEEE
  • Double ion implanted V-MOS technology

    Page(s): 3 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 μm) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-Å gate oxide thickness. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Josephson nonlatching logic circuits

    Page(s): 73 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Slew induced distortion in operational amplifiers

    Page(s): 39 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    When an operational amplifier is overdriven by a large input signal the output stews. A model has been developed in this paper to predict the influence of slew upon the open-loop and closed-loop frequency response of the operational amplifier. It has been found that, while magnitude distortion occurs in both open- and closed-loop modes, phase distortion only occurs under closed-loop conditions. Experimental and theoretical data compare favorably, demonstrating the accuracy of the model. It is shown that slew induced distortion for the low gain invertor configuration is much larger than for the inverting integrator. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experimental investigation of TRAPATT diode trigger conditions

    Page(s): 14 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2216 KB)  

    Experimental studies have been carried out to determine the mechanisms by which the TRAPATT mode can be triggered into operation in the S-band frequency range. These investigations indicate that the TRAPATT mode can be triggered either by VHF oscillations or by IMPATT oscillations. The various frequencies interact to control the turn-on time and the current required to trigger the diode into oscillation. The interactions between the frequencies is controlled by the microwave and bias circuits. Changing the bias circuit alters the interaction thus causing the turn-on time and trigger current to be different. From this information the necessary bias conditions can be given to reduce the turn-on time and trigger current. With appropriate circuit elements the VHF have been observed to trigger the TRAPATT mode into operation in 5 ns. The IMPATT mode of triggering, however, results in a 20 to 25 ns delay before the TRAPATT signal appears. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generation of transient response of nonlinear bipolar transistor circuits from device fabrication data

    Page(s): 29 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    Dynamic models of double diffused bipolar transistors are generated from device fabrication data. The models consist of interconnections of two- and three-terminal resistors and capacitors whose characteristics are expressed in the form of tabulated values describing piecewise-linear surfaces. A circuit analysis program based on a piecewise-linear approach, simulates the time responses of circuits in which the transistors are imbedded. DC and small-signal AC analyses are also obtained. The computer program package thus yields overall circuit responses with fabrication data as input. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated optical detector array, waveguide, and modulator based on silicon technology

    Page(s): 10 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    An integrated optical (IO) hybrid circuit consisting of a photodetector array, waveguide, and acousto-optic modulator on a common silicon substrate has been fabricated. This IO hybrid circuit is a major step in the development of a combination optical-electronic processing system. In this device an array of p-n junction photodiodes was fabricated on a 2-in silicon wafer and a 7059 glass waveguide film sputtered over an SiO/SUB 2/ insulating layer on the wafer. Another SiO/SUB 2/ layer was deposited under the transducer electrode. The transducer was a 40-MHz lithium niobate rotated Y-cut crystal. A prism was used to couple in the light beam from a 5 mW He-Ne laser. The guided light beam was directed at one of the diodes in the array and pulsed RF signals were applied to the transducer. Oscillator frequencies of 40 MHz and 120 MHz were separately applied. Modulation depths of greater than 25 percent were produced. The fabrication of the optical guide photodiode and electrical interconnections on a single silicon wafer utilized standard IC fabrication techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Harmonic output of class-E RF power amplifiers and load coupling network design

    Page(s): 86 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    Class-E RF power amplifiers have advantages of explicit a priori designability, reproducibility, high efficiency, and low-stress operation of the power output devices. The authors give information on harmonic output and explicit design criteria for harmonic-suppression networks to be used with class-E power amplifiers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experimental confirmation of an analytical model for charge transfer in charge-coupled devices

    Page(s): 45 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    An analytical model for the charge loss as a function of transfer time under low charge levels in surface channel charge-coupled devices has been theoretically determined and experimentally confirmed. The model includes the effect of surface states. A new method of measuring charge transfer makes it possible to determine the role that surface states play in the degradation of signal charge transfer. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computer-aided characterization of differential amplifiers

    Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The performance of various differential amplifier stages is studied using the efficient analysis program based upon the methods of Brodersen and Director (1974). Offset voltage, offset current, and common-mode rejection ratio are all characterized in terms of imbalances in the parameters of the transport model of the transistor. The utility of the program as a design aid is demonstrated through the evaluation of a high-performance differential amplifier stage. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved feedback ECL gate with low delay-power product for the subnanosecond region

    Page(s): 80 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Feedback ECL gates are well suited as basic elements for high-speed LSI circuits. Unfortunately for higher voltage swings, they have a hysteresis which reduces the noise immunity. Here it will be demonstrated theoretically how to remove the hysteresis and how to optimize the transfer characteristic using emitter resistors. For such a gate, a power dissipation of 1.6 mW and a propagation delay time of less than 0.6 ns are evaluated by simulation using the parameters of today's available technologies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Image contour extraction with analog MOS circuit techniques

    Page(s): 65 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB)  

    Simple analog MOS circuits provide real-time contour extraction for video signals from CCD images. Variation in ambient lighting and complexity can be accommodated using novel MOS analog counters. Applications include industrial controls and prosthetics. The possibility of automatic picture focusing is demonstrated with the contour extraction technique developed in this project. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan