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IEEE Journal of Solid-State Circuits

Issue 5 • Oct. 1976

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Displaying Results 1 - 25 of 30
  • [Inside front cover - October 1976]

    Publication Year: 1976, Page(s): f2
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  • Table of contents (October 1976)

    Publication Year: 1976, Page(s): 565
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  • Foreword: Semiconductor Memories

    Publication Year: 1976, Page(s):566 - 567
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  • Foreword: Logic

    Publication Year: 1976, Page(s):568 - 569
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  • A 16 384-bit dynamic RAM

    Publication Year: 1976, Page(s):570 - 574
    Cited by:  Papers (19)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (841 KB)

    A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special... View full abstract»

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  • Charge capacity analysis of the charge-coupled RAM cell

    Publication Year: 1976, Page(s):575 - 585
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1277 KB)

    The charge (or storage) capacity of the dynamic charge-coupled (CC) random access memory (RAM) cell is analyzed. Theoretical expressions for the capacity are developed which provide excellent agreement between theory and experiment. Test devices were operated with typical dynamic metal-oxide-semiconductor (MOS) RAM voltages, and exhibited charge capacities (per unit area) up to 52 and 86 percent o... View full abstract»

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  • A high-speed 16-kbit n-MOS random-access memory

    Publication Year: 1976, Page(s):585 - 590
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of ... View full abstract»

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  • A monostable CMOS RAM with self-refresh mode

    Publication Year: 1976, Page(s):609 - 613
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A development of a new monostable CMOS RAM (MS/RAM) is described. A size of the MS/RAM cell, consisting of a monostable flip-flop and two interconnecting lines instead of a bistable model and three interconnecting lines, is extremely reduced. The static and dynamic behavior of the MS/RAM cell are discussed. Measurements and a computer simulation for the test device exhibited its superior performan... View full abstract»

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  • A 16-kbit nonvolatile charge addressed memory

    Publication Year: 1976, Page(s):631 - 636
    Cited by:  Papers (1)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (745 KB)

    A 16-kbit nonvolatile charge addressed memory (NOVCAM) is described. A unique cell design allows a high-density memory array layout without reduced line widths or spacings. A cell size of 0.5 square mils is produced by a seven mask process with 6-/spl mu/m polysilicon gates, 10-/spl mu/m aluminum gates, and 10-/spl mu/m minimum spacing on all mask levels. Charge addressed write and read operations... View full abstract»

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  • An integrated injection logic (I/sup 2/L) macromodel including lateral and current redistribution effects

    Publication Year: 1976, Page(s):648 - 657
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1147 KB)

    An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required fo... View full abstract»

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  • A low-power, bipolar, two's complement serial pipeline multiplier chip

    Publication Year: 1976, Page(s):669 - 678
    Cited by:  Papers (12)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1158 KB)

    A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with progr... View full abstract»

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  • An associative logic matrix

    Publication Year: 1976, Page(s):679 - 691
    Cited by:  Papers (15)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1531 KB)

    While retaining the regular interconnection structure of read-only memory and programmable logic array devices, associative logic makes possible the efficient realization of multiple output, multilevel, combinational, and sequential networks. The extreme versatility of associative logic is provided by internal feedback and matrix segmentation, both characteristic features of the new device. Intern... View full abstract»

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  • 128-bit multicomparator

    Publication Year: 1976, Page(s):692 - 695
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (609 KB)

    A 128-bit multicomparator was designed to perform the search-sort function on arbitrary length data strings. Devices can be cascaded for longer block lengths or paralleled for bit-parallel, word-serial applications. The circuit utilizes a 3-phase static-dynamic shift register cell for data handling and a unique gated EXCLUSIVE-NOR circuit to accomplish the compare function. The compare operation i... View full abstract»

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  • A 16-bit LSI minicomputer

    Publication Year: 1976, Page(s):696 - 702
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1765 KB)

    A 16-bit LSI minicomputer, using n-channel MOS technology, has been developed. The instruction set contains 126 instructions including floating-point arithmetic and is fully compatible with commercially available minicomputers such as the TOSBAC-40 and the Interdata 70. An execution speed of 2 /spl mu/s is obtained for register to register (RR) instructions. All the central processing unit (CPU) f... View full abstract»

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  • The effect of base contact position on the relative propagation delays of the multiple outputs of an I/sup 2/L gate

    Publication Year: 1976, Page(s):712 - 717
    Cited by:  Papers (10)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The multiple collectors of an I/SUP 2/L gate do not slew simultaneously, giving different propagation delays for the various outputs; the relative positions of the base contact, the injector, and the collector outputs affect these delays. In this paper, three possible configurations are modeled, simulated, and the results summarized. View full abstract»

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  • A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors

    Publication Year: 1976, Page(s):718 - 726
    Cited by:  Papers (44)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (933 KB)

    High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects ... View full abstract»

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  • A two-lump transistor model for computer circuit simulation

    Publication Year: 1976, Page(s):726 - 730
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (590 KB)

    Base resistance is calculated using DC measurements of base current as a function of base-emitter voltage. It is shown that a two-transistor lumped model gives an excellent fit to the measured data. The physical basis for model partitioning and the extension of the model to AC applications is discussed. View full abstract»

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  • [Back inside cover]

    Publication Year: 1976, Page(s): b1
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    Freely Available from IEEE
  • Two 4K static 5-V RAM's

    Publication Year: 1976, Page(s):602 - 609
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    This paper describes two 4096-bit, static, TTL compatible, 5 V only, MOS RAM's with worst case access times down to 200 ns and worst case power dissipations down to 370 mW. One is organized as 1K×4 and the other as 4K×1. Both devices are obtained from the same 192- by 197-mil die by a metal mask option and both are assembled in 22-pin dual-in-line packages. A novel memory status output... View full abstract»

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  • Instabilities in RF-power amplifiers caused by a self-oscillation in the transistor bias network

    Publication Year: 1976, Page(s):703 - 712
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    This paper describes a self-oscillation in the bias network of an amplifier which is commonly used for the output stage in mobile transmitters. It is demonstrated how some often observed spurious oscillations may be related to the self-oscillation and a method for stabilizing the amplifier is derived and discussed. View full abstract»

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  • VMOS ROM

    Publication Year: 1976, Page(s):614 - 622
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2064 KB)

    A new v-groove MOS (VMOS) read-only memory (ROM) is presented. The static 16-kbit ROM operates from a single 5-V supply, features typical and worst case access times of 160 ns and 200 ns, respectively, and has a die size of 120×140 mil/SUP 2/ using 6-μm design rules. The purposes for fabricating the VMOS ROM are to demonstrate the large-scale integration (LSI) yield feasibility of the VMO... View full abstract»

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  • The behavior of the continuously charge-coupled random-access memory (C/SUP 3/RAM)

    Publication Year: 1976, Page(s):591 - 596
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    This paper describes a new random-access memory which achieves a bit density comparable to CCD memories. This memory uses as storage elements single-transistor memory cells which are connected to a common bit line. The bit line is implemented with an MOS transmission line, which makes possible an almost lossless charge transport from the single-transistor memory cell to the read/write amplifier. D... View full abstract»

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  • Mini-MSINC-a minicomputer simulator for MOS circuits with modular built-in model

    Publication Year: 1976, Page(s):730 - 732
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    This correspondence describes Mini-MSINC, a minicomputer simulator for metal-oxide-semiconductor (MOS) integrated nonlinear circuits. Mini-MSINC runs on a HP2100-series minicomputer with 32K words of memory and simulates the nonlinear d.c. and transient responses of MOS transistor circuits. A test circuit of 26 transistors with 150 time points was simulated in 10 min. A modular-model program featu... View full abstract»

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  • High sensitivity charge-transfer sense amplifier

    Publication Year: 1976, Page(s):596 - 601
    Cited by:  Papers (41)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    A balanced charge-transfer sense amplifier for one-device cell memory arrays is presented. Charge-transfer techniques are used to preamplify the sense signal and to isolate the large bit/sense (B/S) line capacitance from the nodes of a dynamic latch. The high sensitivity of the sense-refresh amplifier is demonstrated in an experimental memory array with a B/S line to ell storage node capacitance r... View full abstract»

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  • Energy per logic operation in integrated circuits: definition and determination

    Publication Year: 1976, Page(s):657 - 661
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator me... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com