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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Aug. 1976

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Displaying Results 1 - 25 of 26
  • [Inside front cover - August 1976]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1976)

    Page(s): 429
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    Freely Available from IEEE
  • Foreword: Special Issue on Technology and Processing for Integrated Circuits

    Page(s): 430
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    Freely Available from IEEE
  • Complementary DMOS process for LSI

    Page(s): 453 - 458
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    This paper describes a new complementary metal-oxide semiconductor (CMOS) integrated circuit technology that utilizes a symmetrical double-diffused n-channel transistor. The features of the technology are the use of five masks, a self-aligned p-well diffusion and short channel n-MOS transistors. This results in a fifty percent reduction in p-well area as compared to conventional CMOS devices and lowers processing costs. Integrated circuits, fabricated using boron implantation for the p-well dose and p/SUP +/ diffusion, and arsenic implantation for the n/SUP +/ diffusion, exhibit a p-channel threshold of -1.8 V and an n-channel threshold of 1.2 V. The n-channel threshold is controlled by an initial boron implant of 3/spl times/10/SUP 14/ cm/SUP -2/ and subsequent double-diffusion steps. An invertor chain of seven cells bas been operated with a supply of 3-11 V. In operation, the delay per stage was 13 ns at 5 V and 5 ns at 10 V. View full abstract»

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  • A high power MOSFET with a vertical drain electrode and a meshed gate structure

    Page(s): 472 - 477
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    A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor. View full abstract»

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  • Processing technology and AC/DC characteristics of linear compatible I/sup 2/L

    Page(s): 478 - 485
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    The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, processing, and device performance are presented for I/SUP 2/L structures built on several different types of material. The I/SUP 2/L performance achieved in the linear compatible technology easily allowed a fan-out of four and gate propagation delay less than 50 ns with standard device breakdowns of 20 V; but fan-out is limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns. View full abstract»

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  • A new bipolar process-borsenic

    Page(s): 495 - 500
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    A novel bipolar process, with arsenic emitters, has been developed. The base and the emitter are simultaneously diffused from an oxide source containing B/SUB 2/O/SUB 3/ and As/SUB 2/O/SUB 3/. Because of the slow diffusion of B in the presence of As, extremely shallow junctions have been obtained. n-p-n transistors with high h/SUB FE/, high breakdown, high f/SUB T/, and very little low current h/SUB FE/ falloff have been fabricated. Lateral p-n-p and p-channel JFET's have also been fabricated on the same chip without any extra processing step. View full abstract»

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  • A vertical channel JFET fabricated using silicon planar technology

    Page(s): 511 - 518
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    A vertical channel JFET with a new structure was fabricated using a self-aligned process and doped polysilicon technology. This structure is suitable for a high power device, since many channels are easily integrated on a single chip. It is also suitable for a high frequency device, because two essential conditions for high frequency operation, sufficiently low gate resistance and small channel length, can be realized without difficulty. This device shows triode-like I-V characteristics, which are determined by the channel impurity concentration and gate diffusion profile. Typical performances of an n-channel, 4 mm/spl times/4 mm, 5520 channel power FET, designed for an audio amplifier, are a voltage amplification factor of 5, a source-to-gate breakdown voltage of 60 V, a drain-to-gate breakdown voltage of 200 V, and I/SUB DSS/=4 A at V/SUB DS/=7 V. View full abstract»

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  • Multilevel random-access memory using one transistor per cell

    Page(s): 519 - 528
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    A memory cell capable of storing multilevel or analog information and providing random-access operation with nondestructive readout has been studied. It uses a single junction field-effect transistor (JFET) as the storage cell. Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/SUP 2/. Tracking voltage and current reference circuitry is used to accommodate variations in fabrication processing and operating temperature. View full abstract»

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  • Antiblooming: A new approach for linear imagers

    Page(s): 547 - 550
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    A new solution for a linear imager with antiblooming is presented. The overload-generated charge spills over a potential barrier into a CCD, called overflow CCD, wherein that charge is transferred to an output and eliminated. The information charge, integrated under the sensor electrodes, is transferred across this overflow CCD into a second CCD, called the readout CCD. The principle of the operation of this imager is explained and preliminary experimental results are given. View full abstract»

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  • A low-pass biquad derived filter realization

    Page(s): 552 - 555
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    A biquad derived structure employing two Norton (current differencing) amplifiers is presented which requires the minimum number of components. Transfer characteristics of the form K/SUB 1//D(S) and K/SUB 2/(S+/spl omega//SUB n//Q)/D(S) with D(S)=S/SUP 2/+/spl omega//SUB n/S/Q+/spl omega//SUB n//SUP 2/ are realized. Biasing constraints are of major importance in the detailed realization and a typical circuit design is presented along with a discussion of its performance, which is compared with that of others. View full abstract»

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  • [Back inside cover]

    Page(s): b1
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    Freely Available from IEEE
  • Metallization for integrated circuits using a lift-off technique

    Page(s): 466 - 471
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    A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-μm gaps between metal conductors can be obtained even at 0.8-μm metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrographs of Al/Si conductor patterns are presented. View full abstract»

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  • Modular single-stage universal logic gate

    Page(s): 529 - 538
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    First and second generation universal logic gate (ULG):IC's are described. The ULG comprises one-stage arrays of two identical cascade circuits. These ULG's are shown to realize all logic functions of four (and fewer) input variables in approximately the same propagation delay as a single ECL current switch emitter follower (CSEF) gate fabricated with the same processing technology. Substantial power and power-delay product advantages relative to CSEF arrays are demonstrated at comparable silicon area for realization of all four-input functions. The ULG was developed for implementing logic arrays with a minimum number of gating stages. View full abstract»

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  • On the analysis of nonlinear resistive networks considering the effect of temperature

    Page(s): 550 - 552
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    In this correspondence a new method is presented for the analysis of nonlinear resistive networks considering the effect of the dissipated-power-dependent inner temperature of electronic devices on the electrical behaviour of circuits. It is shown that this consideration is only possible if the equations of the electrical network are extended by equations of the corresponding thermal network of the circuit and if all equations together are solved simultaneously. The temperature is introduced as variable and not as a parameter. View full abstract»

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  • LSI multiplier using high speed ULG

    Page(s): 539 - 544
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    The three-gating stage 4×4-bit multiplier design and its LSI realization using 34 ECL cascode cells are described. Use of a modular single-stage universal logic gate as the primary logic building block in the multiplier allows achievement of a factor of 2 delay reduction relative to multipliers described previously. View full abstract»

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  • High frequency response of inverting integrators

    Page(s): 545 - 547
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    Inverting integrators are dependent upon the open-loop frequency response of the amplifier. Improvement in frequency performance of an order of magnitude is achieved with two-pole versus single-pole compensation for the same amplifier. Amplifier output impedance can affect integrator frequency response. View full abstract»

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  • Measurement of V/SUB CE(sat)/ of RF power transistors and of waveform details near V/SUB CE(sat)/

    Page(s): 555 - 557
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    Accurate measurement of V/SUB CE(sat)/ in RF operation and of the waveform details near V/SUB CE(sat)/ requires that the oscilloscope vertical deflection sensitivity be high enough so that the waveform peak value would drive the amplifier far off-scale. With many oscilloscopes, the deflection amplifier does not recover fast enough for the resulting on-screen display to be undistorted. The wideband waveform clipper described allows accurate measurement of V/SUB CE(sat)/ and the waveform details near V/SUB CE(saT)/ without overloading the oscilloscope vertical deflection amplifier. View full abstract»

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  • Unifying the concepts of offset voltage and common-mode rejection ratio [bipolar differential amplifiers]

    Page(s): 557 - 561
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    A unified treatment of offset voltage and common-mode rejection ratio (CMRR) of bipolar differential amplifiers using large signal models is presented. The offset voltage expressions for the differential pair and 741 stages are first calculated in terms of transport model parameters. CMRR may then be calculated from these expressions. Two distinct mechanisms contributing to CMRR are identified. View full abstract»

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  • Ion-implanted super-grain transistors

    Page(s): 485 - 491
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    This paper discusses the use of ion implantation to develop a viable high-yielding process for fabricating super-gain transistors for integrated circuits. The authors discuss the fabrication processes utilized, the pertinent device physics, the manufacturing tradeoffs, and present the results obtained for two different ion-implanted base integrated-circuit processes. View full abstract»

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  • Emitter-collector shorts in bipolar devices

    Page(s): 505 - 510
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    Although emitter-collector shorts may result from a number of processing problems, the phenomenon known as `pipes' represents one of the most interesting and most troublesome sources of such electrical shorts in bipolar circuits. In this review paper, several observations on the nature and causes of pipes are discussed, as well as means to evaluate their incidence and to control their occurrence. View full abstract»

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  • High-voltage SOS/MOS devices and circuit elements: Design, fabrication, and performance

    Page(s): 431 - 442
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    High-voltage metal-oxide-semiconductor (HVMOS) transistors fabricated with low-voltage MOS circuits on the same silicon-on-sapphire (SOS) chip are critical for EAROM's and plasma display applications. An examination of the voltage limitations in conventional MOS is described. Several approaches to fabricating HVMOS transistors are analyzed, including the MOS tetrode, the extended drain MOST, and the double diffused MOST. Results of parameter tests on these devices are given and characteristics of HVMOS circuit elements discussed. View full abstract»

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  • Process technology for radiation-hardened CMOS integrated circuits

    Page(s): 459 - 465
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    A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing. View full abstract»

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  • Laser coding of bipolar read-only memories

    Page(s): 500 - 505
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    Laser beam coding of high-speed bipolar silicon integrated circuit memories is described. Coding is accomplished by the selective vaporization of Ti-Pt links connecting the contact pads of each memory cell to Ti-Pt-Au bit lines. Vaporized link resistances of >10/SUP 9/ Ω can be consistently obtained, with no melting of the adjacent gold patterns. Parameters that have been found to be relevant to the link vaporization process are described including the number of laser pulses per link, beam spot size, thickness of the gold metallization, and pulse energy. The laser coding process is especially useful for applications where relatively small numbers of chips of each of many codes are needed, since only one photolithographic mask set is required. View full abstract»

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  • High-performance transistors with arsenic-implanted polysil emitters

    Page(s): 491 - 495
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    Integrated high-frequency transistors (f/SUB T/>3 GHz) with an arsenic implanted polysil emitter have been investigated. The results are compared with data of bipolar transistors made with the conventional planar technique. It is shown that better emitter efficiency higher current carrying capability, and improved emitter-base breakdown can be achieved for transistors with polysil emitters. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan