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IEEE Journal of Solid-State Circuits

Issue 4 • Date Aug. 1976

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Displaying Results 1 - 25 of 26
  • [Inside front cover - August 1976]

    Publication Year: 1976, Page(s): f2
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    Freely Available from IEEE
  • Table of contents (August 1976)

    Publication Year: 1976, Page(s): 429
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    Freely Available from IEEE
  • Foreword: Special Issue on Technology and Processing for Integrated Circuits

    Publication Year: 1976, Page(s): 430
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    Freely Available from IEEE
  • Complementary DMOS process for LSI

    Publication Year: 1976, Page(s):453 - 458
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    This paper describes a new complementary metal-oxide semiconductor (CMOS) integrated circuit technology that utilizes a symmetrical double-diffused n-channel transistor. The features of the technology are the use of five masks, a self-aligned p-well diffusion and short channel n-MOS transistors. This results in a fifty percent reduction in p-well area as compared to conventional CMOS devices and l... View full abstract»

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  • A high power MOSFET with a vertical drain electrode and a meshed gate structure

    Publication Year: 1976, Page(s):472 - 477
    Cited by:  Papers (16)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB)

    A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel... View full abstract»

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  • Processing technology and AC/DC characteristics of linear compatible I/sup 2/L

    Publication Year: 1976, Page(s):478 - 485
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (667 KB)

    The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, pr... View full abstract»

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  • A new bipolar process-borsenic

    Publication Year: 1976, Page(s):495 - 500
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB)

    A novel bipolar process, with arsenic emitters, has been developed. The base and the emitter are simultaneously diffused from an oxide source containing B/SUB 2/O/SUB 3/ and As/SUB 2/O/SUB 3/. Because of the slow diffusion of B in the presence of As, extremely shallow junctions have been obtained. n-p-n transistors with high h/SUB FE/, high breakdown, high f/SUB T/, and very little low current h/S... View full abstract»

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  • A vertical channel JFET fabricated using silicon planar technology

    Publication Year: 1976, Page(s):511 - 518
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1553 KB)

    A vertical channel JFET with a new structure was fabricated using a self-aligned process and doped polysilicon technology. This structure is suitable for a high power device, since many channels are easily integrated on a single chip. It is also suitable for a high frequency device, because two essential conditions for high frequency operation, sufficiently low gate resistance and small channel le... View full abstract»

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  • Multilevel random-access memory using one transistor per cell

    Publication Year: 1976, Page(s):519 - 528
    Cited by:  Papers (4)  |  Patents (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1038 KB)

    A memory cell capable of storing multilevel or analog information and providing random-access operation with nondestructive readout has been studied. It uses a single junction field-effect transistor (JFET) as the storage cell. Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/... View full abstract»

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  • Antiblooming: A new approach for linear imagers

    Publication Year: 1976, Page(s):547 - 550
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (749 KB)

    A new solution for a linear imager with antiblooming is presented. The overload-generated charge spills over a potential barrier into a CCD, called overflow CCD, wherein that charge is transferred to an output and eliminated. The information charge, integrated under the sensor electrodes, is transferred across this overflow CCD into a second CCD, called the readout CCD. The principle of the operat... View full abstract»

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  • A low-pass biquad derived filter realization

    Publication Year: 1976, Page(s):552 - 555
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (427 KB)

    A biquad derived structure employing two Norton (current differencing) amplifiers is presented which requires the minimum number of components. Transfer characteristics of the form K/SUB 1//D(S) and K/SUB 2/(S+/spl omega//SUB n//Q)/D(S) with D(S)=S/SUP 2/+/spl omega//SUB n/S/Q+/spl omega//SUB n//SUP 2/ are realized. Biasing constraints are of major importance in the detailed realization and a typi... View full abstract»

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  • [Back inside cover]

    Publication Year: 1976, Page(s): b1
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    Freely Available from IEEE
  • Unifying the concepts of offset voltage and common-mode rejection ratio [bipolar differential amplifiers]

    Publication Year: 1976, Page(s):557 - 561
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A unified treatment of offset voltage and common-mode rejection ratio (CMRR) of bipolar differential amplifiers using large signal models is presented. The offset voltage expressions for the differential pair and 741 stages are first calculated in terms of transport model parameters. CMRR may then be calculated from these expressions. Two distinct mechanisms contributing to CMRR are identified. View full abstract»

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  • Measurement of V/SUB CE(sat)/ of RF power transistors and of waveform details near V/SUB CE(sat)/

    Publication Year: 1976, Page(s):555 - 557
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Accurate measurement of V/SUB CE(sat)/ in RF operation and of the waveform details near V/SUB CE(sat)/ requires that the oscilloscope vertical deflection sensitivity be high enough so that the waveform peak value would drive the amplifier far off-scale. With many oscilloscopes, the deflection amplifier does not recover fast enough for the resulting on-screen display to be undistorted. The wideband... View full abstract»

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  • Ion-implanted super-grain transistors

    Publication Year: 1976, Page(s):485 - 491
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    This paper discusses the use of ion implantation to develop a viable high-yielding process for fabricating super-gain transistors for integrated circuits. The authors discuss the fabrication processes utilized, the pertinent device physics, the manufacturing tradeoffs, and present the results obtained for two different ion-implanted base integrated-circuit processes. View full abstract»

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  • Optimum load device for DMOS integrated circuits

    Publication Year: 1976, Page(s):443 - 452
    Cited by:  Papers (1)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1752 KB)

    Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation, <1,1,1> crystal orientation should be used. The <1,1,1> crystal orientation also yields a higher transconductance for the DMOS transistor than the <1,0,0&... View full abstract»

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  • On the analysis of nonlinear resistive networks considering the effect of temperature

    Publication Year: 1976, Page(s):550 - 552
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    In this correspondence a new method is presented for the analysis of nonlinear resistive networks considering the effect of the dissipated-power-dependent inner temperature of electronic devices on the electrical behaviour of circuits. It is shown that this consideration is only possible if the equations of the electrical network are extended by equations of the corresponding thermal network of th... View full abstract»

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  • High-voltage SOS/MOS devices and circuit elements: Design, fabrication, and performance

    Publication Year: 1976, Page(s):431 - 442
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    High-voltage metal-oxide-semiconductor (HVMOS) transistors fabricated with low-voltage MOS circuits on the same silicon-on-sapphire (SOS) chip are critical for EAROM's and plasma display applications. An examination of the voltage limitations in conventional MOS is described. Several approaches to fabricating HVMOS transistors are analyzed, including the MOS tetrode, the extended drain MOST, and t... View full abstract»

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  • Metallization for integrated circuits using a lift-off technique

    Publication Year: 1976, Page(s):466 - 471
    Cited by:  Papers (20)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-μm gaps between metal conductors can be obtained even at 0.8-μm metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrograph... View full abstract»

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  • High frequency response of inverting integrators

    Publication Year: 1976, Page(s):545 - 547
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Inverting integrators are dependent upon the open-loop frequency response of the amplifier. Improvement in frequency performance of an order of magnitude is achieved with two-pole versus single-pole compensation for the same amplifier. Amplifier output impedance can affect integrator frequency response. View full abstract»

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  • Laser coding of bipolar read-only memories

    Publication Year: 1976, Page(s):500 - 505
    Cited by:  Papers (10)  |  Patents (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    Laser beam coding of high-speed bipolar silicon integrated circuit memories is described. Coding is accomplished by the selective vaporization of Ti-Pt links connecting the contact pads of each memory cell to Ti-Pt-Au bit lines. Vaporized link resistances of >10/SUP 9/ Ω can be consistently obtained, with no melting of the adjacent gold patterns. Parameters that have been found to be rele... View full abstract»

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  • Modular single-stage universal logic gate

    Publication Year: 1976, Page(s):529 - 538
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    First and second generation universal logic gate (ULG):IC's are described. The ULG comprises one-stage arrays of two identical cascade circuits. These ULG's are shown to realize all logic functions of four (and fewer) input variables in approximately the same propagation delay as a single ECL current switch emitter follower (CSEF) gate fabricated with the same processing technology. Substantial po... View full abstract»

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  • High-performance transistors with arsenic-implanted polysil emitters

    Publication Year: 1976, Page(s):491 - 495
    Cited by:  Papers (57)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Integrated high-frequency transistors (f/SUB T/>3 GHz) with an arsenic implanted polysil emitter have been investigated. The results are compared with data of bipolar transistors made with the conventional planar technique. It is shown that better emitter efficiency higher current carrying capability, and improved emitter-base breakdown can be achieved for transistors with polysil emitters. View full abstract»

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  • Process technology for radiation-hardened CMOS integrated circuits

    Publication Year: 1976, Page(s):459 - 465
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology ha... View full abstract»

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  • Emitter-collector shorts in bipolar devices

    Publication Year: 1976, Page(s):505 - 510
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    Although emitter-collector shorts may result from a number of processing problems, the phenomenon known as `pipes' represents one of the most interesting and most troublesome sources of such electrical shorts in bipolar circuits. In this review paper, several observations on the nature and causes of pipes are discussed, as well as means to evaluate their incidence and to control their occurrence. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com