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IEEE Journal of Solid-State Circuits

Issue 3 • Date June 1976

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Displaying Results 1 - 22 of 22
  • [Inside front cover - June 1976]

    Publication Year: 1976, Page(s): f2
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  • Table of contents (June 1976)

    Publication Year: 1976, Page(s): 349
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  • Introduction from the First European Solid-State Circuits Conference Chairman

    Publication Year: 1976, Page(s): 350
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  • Foreword: Special Issue on the First European Solid-State Circuits Conference (ESSCIRC)

    Publication Year: 1976, Page(s): 351
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  • A high performance low power 2048-bit memory chip in MOSFET technology and its application

    Publication Year: 1976, Page(s):352 - 359
    Cited by:  Papers (3)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB)

    A static 2048-bit read/wire memory chip for main stores is described. It uses a modified 6-device memory cell in an n-channel MOSFET technology. To exploit the potential of the given MOSFET technology with respect to the cost/performance ratio and the power-delay product, special provisions are taken. The power is kept low by the gate driver concept as well as by clocked peripheral circuits. High ... View full abstract»

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  • High-speed static programmable logic array in LOCMOS

    Publication Year: 1976, Page(s):365 - 369
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1041 KB)

    A large static programmable logic array (PLA) with 20 inputs, 94 product terms, and 24 outputs, designed and realized in LOCMOS, the complementary MOS technology with isolation by local oxidation of silicon. Layout and physical parameters of this technology resulted in a simple, dense, and low-capacity design. The dc and transient features of different realization possibilities have been simulated... View full abstract»

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  • High speed integrated injection logic (I/sup 2/L)

    Publication Year: 1976, Page(s):379 - 385
    Cited by:  Papers (29)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB)

    High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-... View full abstract»

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  • A subnanosecond integrated switching circuit with MESFET's for LSI

    Publication Year: 1976, Page(s):385 - 394
    Cited by:  Papers (14)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented... View full abstract»

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  • Active bipolar transistor solid-state crosspoints

    Publication Year: 1976, Page(s):394 - 400
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (886 KB)

    The new principle of an active crosspoint for telecommunications traffic exchanges is explained. Its basic difference concerns the application of device gain to obtain more favorable on-state specifications. The realization of this principle has resulted in a stable circuit which is insensitive to transients and temperature variations. This circuit also provides good off-state specifications and b... View full abstract»

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  • An integrated wide-tunable sine oscillator

    Publication Year: 1976, Page(s):401 - 403
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Describes a two-integrator sine oscillator which features independent control of frequency and damping and a lack of spurious responses and is integrable as a monolithic IC. The circuitry of this oscillator is discussed. The following experimental results were found: electronical, continuous tunability over four frequency decades, frequency shifting over at least one decade without amplitude devia... View full abstract»

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  • An integrated bandgap reference

    Publication Year: 1976, Page(s):403 - 406
    Cited by:  Papers (12)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load curre... View full abstract»

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  • A precision active current-splitting circuit technique

    Publication Year: 1976, Page(s):406 - 408
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The interconnection of a modified Wilson current mirror-operating in the emitter-drive mode-an operational amplifier and a matched field-effect transistor (FET) pair realizes an analog current divider that splits a d.c. input current, I, into two parts that are equal to within /spl plusmn/0.4 percent, for 2 /spl mu/A<I<2 mA. The incremental output resistance is in the G/spl Omega/ region. Th... View full abstract»

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  • An All-MOS Analog-to-Digital converter using a constant slope approach

    Publication Year: 1976, Page(s):408 - 410
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (314 KB)

    A novel circuit configuration for indirect or slope-type analog-to-digital converters (ADC's) is described. Due to the simplicity of the analog requirements, this technique lends itself to implementation in a single low-cost single-polarity MOS chip. A breadboard version has been operated with 11 bit accuracy at a sample rate of 20/s. View full abstract»

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  • A model for charge transport in surface channel devices

    Publication Year: 1976, Page(s):422 - 424
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB)

    A distributed capacitor model is proposed to simulate charge transport in surface inversion layers. Theoretical results of this model agreed well with experimental results obtained on the input section of a charge-coupled device (CCD). View full abstract»

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  • A proposed distributed Josephson logic circuit

    Publication Year: 1976, Page(s):424 - 426
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (334 KB)

    A new Josephson logic circuit is proposed with spatially distributed inputs and outputs. It is uniquely suited to picosecond functional logic arrays, memory peripheral circuits, and other applications requiring large distributed fan-in. View full abstract»

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  • [Back inside cover]

    Publication Year: 1976, Page(s): b1
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  • The differential pair as a triangle-sine wave converter

    Publication Year: 1976, Page(s):418 - 420
    Cited by:  Papers (31)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The performance of a differential pair with emitter degeneration as a triangle-sine wave converter is analyzed. Equations describing the circuit operation are derived and solved both analytically and by computer. This allows selection of operating conditions for optimum performance such that total harmonic distortion as low as 0.2 percent has been measured. View full abstract»

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  • Common-mode rejection limitations of differential amplifiers

    Publication Year: 1976, Page(s):411 - 417
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The common-mode rejection ratio (CMRR) equations of the differential pair and differential cascade amplifiers are reformulated in terms of imbalances in the saturation current. Early voltage, and current gain parameters of the transport model of the bipolar transistor. The effect of source resistance on CMRR is included in the formulation. The CMRR of this class of amplifier is shown to be limited... View full abstract»

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  • High-speed programmable logic arrays in ESFI SOS technology

    Publication Year: 1976, Page(s):370 - 374
    Cited by:  Papers (2)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Exploratory MOS programmable logic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silicon films on insulators (ESFI) silicon-on-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are... View full abstract»

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  • Minimum size ROM structure compatible with silicon-gate E/D MOS LSI

    Publication Year: 1976, Page(s):360 - 364
    Cited by:  Papers (8)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    Describes a new read-only memory (ROM) with minimum geometry. A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs. The content of a memory cell in the new ROM is determined by the choice of the MOST threshold mode, either an enhancement or depletion mode; this diffe... View full abstract»

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  • Integrated TV tuning system

    Publication Year: 1976, Page(s):420 - 422
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper presents a frequency synthesized digital tuning system for UHF/VHF TV receivers and the integrated circuits developed to implement this scheme. The design and performance of the GHz÷248/256 programmable prescaler is described in detail. View full abstract»

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  • On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

    Publication Year: 1976, Page(s):374 - 378
    Cited by:  Papers (749)  |  Patents (118)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have bee... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com