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IEEE Journal of Solid-State Circuits

Issue 5 • Date Oct. 1974

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Displaying Results 1 - 21 of 21
  • [Front cover - October 1974]

    Publication Year: 1974, Page(s): f1
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    Freely Available from IEEE
  • [Inside front cover - October 1974]

    Publication Year: 1974, Page(s): f2
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  • Editor's Note (October 1974)

    Publication Year: 1974, Page(s): 205
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    Freely Available from IEEE
  • Foreword - Special Issue on Semiconductor Memory and Logic

    Publication Year: 1974, Page(s):205 - 206
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    Freely Available from IEEE
  • A 25-ns read access bipolar 1 kbit TTL RAM

    Publication Year: 1974, Page(s):283 - 284
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB)

    Design considerations are described for a fast and compact 1024-bit TTL RAM based upon the nonsaturating operation of transistors that has small but stable levels and swings by virtue of `digital resistances'. It is well matched with the very fine pattern processes currently achieved both for metalization and diffusion. View full abstract»

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  • A quality measure for LSI components

    Publication Year: 1974, Page(s):291 - 297
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (762 KB)

    Large-scale integration components are subjected to testing based on stuck fault modeling. Stuck fault testing often does not provide patterns for all possible stuck conditions that can exist in a circuit. Because of the incompleteness of test coverage, a new quality measure is needed-one that is not based on sample inspection. Such an LSI quality measure is described in this paper. The LSI qualit... View full abstract»

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  • An integrated m-out-of-n detection circuit using threshold logic

    Publication Year: 1974, Page(s):297 - 306
    Cited by:  Papers (10)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1302 KB)

    The design of the integrated 4-out-of-9 detector is based on a threshold logic approach. A differential current-switching circuit configuration is used, and the detector is fully compatible with conventional emitter-coupled logic (ECL). The circuit has a propagation delay of 16 ns and dissipates only 100 mW. The functional power-delay product of 1600 pJ is an order of magnitude below that achieved... View full abstract»

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  • On the trigger delay of avalanche transistors

    Publication Year: 1974, Page(s):307 - 309
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    An explanation of the triggering delay in avalanche transistors is given, based on the results of a numerical model for the avalanche transistor. The results obtained allow one to modify the delay by very simple means as it is needed when several avalanche stages are paralleled. View full abstract»

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  • [Back inside cover]

    Publication Year: 1974, Page(s): b1
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  • VMOS: high speed TTL compatible MOS logic

    Publication Year: 1974, Page(s):239 - 250
    Cited by:  Papers (36)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1712 KB)

    VMOS is a new v-groove n-channel MOS logic structure well suited for 5-V high-speed random logic. Compared to a typical gold-doped TTL medium-scale integrated (MSI) circuit, an experimental pin for pin equivalent VMOS circuit is 20 percent faster, four times smaller in area, and six times lower in power dissipation. On-chip VMOS delays are in the 2-3 ns range; off-chip drive capability exceeds 50 ... View full abstract»

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  • Design of ion-implanted MOSFET's with very small physical dimensions

    Publication Year: 1974, Page(s):256 - 268
    Cited by:  Papers (1239)  |  Patents (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB)

    This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain re... View full abstract»

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  • Femtojoule Josephson tunneling logic gates

    Publication Year: 1974, Page(s):277 - 282
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The design of Josephson tunneling logic (JTL) gates capable of performing the logic functions of AND, OR, INVERT and CARRY is considered. The design equations were solved for a rectangular Josephson junction in which the geometry was adjusted to ensure that all logical inputs were equivalent. Experimental JTL gates were found to operate with a logic delay of less than 200 ps, and with a power-dela... View full abstract»

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  • Optimum linear filtering for charge-transfer devices

    Publication Year: 1974, Page(s):285 - 291
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    A method of filtering analog signals transferred through a charge-transfer device (CTD), which is capable of greatly reducing the distortion introduced by incomplete charge transfer, is suggested. By using transversal filters consisting in part of single CTD storage cells to achieve the necessary phase delay, the output charge packets can be combined in a manner which offsets the presence of incom... View full abstract»

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  • High-density static ESFI MOS memory cells

    Publication Year: 1974, Page(s):234 - 238
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 μm/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells k... View full abstract»

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  • The injection model-a structure-oriented model for merged transistor logic (MTL)

    Publication Year: 1974, Page(s):218 - 227
    Cited by:  Papers (86)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The merged transistor device is represented by assigning separate diodes to the various electron and hole injections along the active p-n junction. Where collection takes place, current sources are introduced. Measurement procedures are described that allow a quantitative separation of the various injections, and hence the determination of the model parameters. Results of such measurements are giv... View full abstract»

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  • Ion-implanted ESFI MOS devices with short switching times

    Publication Year: 1974, Page(s):250 - 256
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Switching times of complementary MOS devices realized with epitaxial silicon films on insulators (ESFI) are reduced by using a self-aligning technique with ion implantation, since the gate overlapping capacitances and therefore the so-called Miller capacitances, are reduced thereby. Switching times and power dissipation have been measured using multistage ring oscillators. Stage-delay times of 500... View full abstract»

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  • High-speed integrated logic with GaAs MESFET's

    Publication Year: 1974, Page(s):269 - 276
    Cited by:  Papers (76)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The feasibility of using GaAs metal-semiconductor field-effect transistors (GaAs MESFET's) in fast switching and high-speed digital integrated circuit applications is demonstrated. GaAs MESFET's with 1-μm gate length are shown to have a current-gain-bandwidth product f/SUB T/ equal to 15 GHz. These devices exhibit a 15 ps internal delay in a large-signal switching test. A simple logic circuit c... View full abstract»

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  • Current hogging logic (CHL)-a new bipolar logic for LSI

    Publication Year: 1974, Page(s):228 - 233
    Cited by:  Papers (8)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Logic functions of current hogging logic (CHL) are established by switching the lateral injection current in intermediate collector p-n-p structures. High functional density is achieved, since NOR, NAND, and complex gates can readily be realized and all logic elements can be placed within a common isolation region. CHL is fabricated with a standard buried collector process, and hence is compatible... View full abstract»

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  • Integrated injection logic-present and future

    Publication Year: 1974, Page(s):206 - 211
    Cited by:  Papers (27)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic... View full abstract»

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  • Frequency response of a multiplexed charge-transfer delay line

    Publication Year: 1974, Page(s):310 - 311
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Analytic expressions for the frequency response of multiplexed charge-transfer devices (MCTD's) are derived. A brief discussion of the advantages and disadvantages of several CTD architectures is given. View full abstract»

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  • Terminal-oriented model for merged transistor logic (MTL)

    Publication Year: 1974, Page(s):211 - 217
    Cited by:  Papers (43)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com