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IEEE Journal of Solid-State Circuits

Issue 4 • Date Aug. 1973

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Displaying Results 1 - 12 of 12
  • [Front cover - August 1973]

    Publication Year: 1973, Page(s): f1
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    Freely Available from IEEE
  • [Inside front cover - August 1973]

    Publication Year: 1973, Page(s): f2
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    Freely Available from IEEE
  • A dynamic delay line with a bipolar one-transistor cell

    Publication Year: 1973, Page(s):251 - 259
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1557 KB)

    A new bipolar one-transistor cell for the storage of analog information is described. This cell forms the basis of a 256-sample dynamic delay line, where 16/spl times/16 cells of a two-dimensional array are successively accessed. The circuitry for the generation of the selection voltages is specially designed in order to make the power dissipation independent of the size of the delay line. View full abstract»

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  • A 24x6 interlaced-scan MOS image sensor

    Publication Year: 1973, Page(s):286 - 289
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB)

    A new 24/spl times/6 self-scanned MOS image sensor has been developed for the Optacon reading aid for the blind. This new image sensor has a unique circuit design that provides in a simple manner interlaced row scanning and low-light level detection. While a previous investigation (1969) showed that self-scanned MOS image sensors are capable of operating with illumination levels of 1 /spl mu/W/cm/... View full abstract»

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  • Accurate metallization capacitances for integrated circuits and packages

    Publication Year: 1973, Page(s):289 - 290
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB)

    The parallel-plate formula is widely used by the solid-state circuit designer to estimate capacitances in integrated circuits. Since considerable errors may result from using this approximation, this correspondence gives correction curves for a wide range of parameters. It is shown that the finite conductor thickness may significantly contribute to the increase in capacitance. View full abstract»

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  • Correction to "Noise Performance of Low-Sensitivity Active Filters"

    Publication Year: 1973, Page(s): 290
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    First Page of the Article
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  • [Back inside cover]

    Publication Year: 1973, Page(s): b1
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    Freely Available from IEEE
  • Distortion in bipolar transistor variable-gain amplifiers

    Publication Year: 1973, Page(s):275 - 282
    Cited by:  Papers (39)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1384 KB)

    Wide-band variable-gain amplifiers consisting of bipolar junction transistors and exhibiting maximum gain larger than unity are considered. The mechanisms of distortion are analyzed at low and high frequencies. Approximate expressions for distortion are derived and give good agreement with computational results and measurements. The most common high-performance variable-gain circuit realizations a... View full abstract»

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  • Design of Schottky-barrier diode clamped transistor layouts

    Publication Year: 1973, Page(s):269 - 275
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB)

    Describes an approach to the design of Schottky-clamped integrated circuit transistor layouts. Three-dimensional distributed resistances are modeled using a grid of lumped resistors. A computer circuit analysis program is used to obtain a simple lumped equivalent circuit for the clamped transistor. The equivalent circuit enables accurate prediction of the useful range of d.c. operating conditions ... View full abstract»

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  • Fast periodic steady-state analysis for large-signal electronic circuits

    Publication Year: 1973, Page(s):260 - 269
    Cited by:  Papers (36)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1656 KB)

    It is shown that current computer-aided circuit analysis programs that are capable of the transient analysis of nonlinear circuits can be modified to include the determination of the periodic steady-state response of large-signal electronic circuits such as class C amplifiers, frequency multipliers, parametric circuits, and oscillators. With this modification only a portion of the transient respon... View full abstract»

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  • Rise time of emitter-coupled logic circuits including the effects of collector-to-base capacitances

    Publication Year: 1973, Page(s):284 - 286
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Rise times of emitter-coupled logic circuits are computed, taking into account collector-to-base capacitances as well as gain-bandwidth products, ohmic base resistances, external stray capacitances, and the finite rise time of the input signal. Basic considerations are discussed, and explicit expressions and graphs are given for a wide range of circuit parameters. View full abstract»

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  • Grounded load complementary FET circuits: Sceptre analysis

    Publication Year: 1973, Page(s):282 - 284
    Cited by:  Papers (3)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The performance of grounded load complementary MOS circuits has been evaluated. It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com