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IEEE Journal of Solid-State Circuits

Issue 5 • Date Oct. 1971

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Displaying Results 1 - 16 of 16
  • [Front cover - October 1971]

    Publication Year: 1971, Page(s): f1
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  • [Inside front cover - October 1971]

    Publication Year: 1971, Page(s): f2
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  • Foreword (October 1971

    Publication Year: 1971, Page(s): 275
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  • A two-terminal transistor memory cell using breakdown

    Publication Year: 1971, Page(s):280 - 283
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (453 KB)

    The features of the cell include easy fabrication, small cell area, large output signals, high-speed Read and Write capability, low average power and inherent immunity to small voltage perturbations. The storage time of the cell is determined by reverse-bias junction leakage and is greater than 10 ns at room temperatures for typical devices. Breakdown degradation of transistors is discussed and a ... View full abstract»

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  • Small-size low-power bipolar memory cell

    Publication Year: 1971, Page(s):283 - 288
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB)

    A d.c.-stable random-access memory (RAM) cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2×3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil2. The cells have been operated at an extremely low d.c. standby power of less than... View full abstract»

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  • A fully decoded 2048-bit electrically programmable FAMOS read-only memory

    Publication Year: 1971, Page(s):301 - 306
    Cited by:  Papers (14)  |  Patents (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (851 KB)

    A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the st... View full abstract»

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  • A memory system based on surface-charge transport

    Publication Year: 1971, Page(s):306 - 313
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1295 KB)

    The surface-charge transistor (SCT) is an integrated-circuit element and involves a new concept for controlling the transfer of stored electrical charge along the surface of a semiconductor. The experimental transient response of a large-geometry SCT is presented. Linear high-density arrays of surface-charge transistors may be utilized to form digital or analog shift registers. The experimental pe... View full abstract»

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  • Comments on "A highly efficient inductorless voltage regulator"

    Publication Year: 1971, Page(s): 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (146 KB)

    See abstr. B9375, C3279 of 1970. A transistor switching regulator has been described that is claimed to be highly efficient. The transformer power loss, which is significant, has been neglected. This is discussed along with several suggestions for improving circuit performance. View full abstract»

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  • Contributors (October 1971)

    Publication Year: 1971, Page(s):335 - 338
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  • [Back inside cover]

    Publication Year: 1971, Page(s): b1
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  • Drift-aiding fringing fields in charge-coupled devices

    Publication Year: 1971, Page(s):322 - 326
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Transverse electric fields at the Si-SiO/SUB 2/ interface (fringing fields) can aid transfer of charge from one potential well to another in charge- coupled devices (CCD). The magnitudes of these drift-aiding fringing fields are evaluated by an approximate analysis and also by computer. The analytical approach assumes zero space charge in the silicon and agrees with the computer solutions in that ... View full abstract»

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  • Some reliability considerations pertaining to LSI technology

    Publication Year: 1971, Page(s):327 - 334
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1696 KB)

    This paper discusses the trends that have developed in LSI, and the requirements for refinements in process technology, closer process control, and improvements in design that are considered to be essential for the full realization of high LSI reliability. Particular attention is paid to advanced multilevel-structure processing and to the use of specially designed test vehicles for purposes of pro... View full abstract»

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  • Main monolithic memory

    Publication Year: 1971, Page(s):276 - 279
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    The 128-bit NDRO random-access memory chip used in the IBM System 370, model 145, and System 7 is described. Consideration is given to packaging power dissipation and systems environment. View full abstract»

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  • Bipolar dynamic memory cell

    Publication Year: 1971, Page(s):297 - 300
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A bipolar dynamic memory cell for use in a high-speed random- access memory consists of a cross-coupled pair of transistors and two diodes. Information is dynamically stored using a bistable charge distribution and must be refreshed at a frequency of 1 kHz by a SELECT operation. Standby power per memory cell is in the nanowatt range. The cell requires only 3 interconnect lines and can be fabricate... View full abstract»

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  • Switched collector impedance memory

    Publication Year: 1971, Page(s):289 - 296
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Bipolar memory cells capable of achieving as high a ratio of READ/WRITE current to standby current as 40:200 in contrast to the ratio of 0.8:8 obtainable by conventional memory cells are proposed. In a standby condition the collector impedance of the cells is high and when accessed the impedance is switched to a much lower value. The proposed device structures proficiently utilize such layers as p... View full abstract»

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  • Charge-coupled digital circuits

    Publication Year: 1971, Page(s):314 - 322
    Cited by:  Papers (31)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1160 KB)

    This paper describes the operation and the applications of charge- coupled shift registers for digital signals. Simple signal-regeneration stages for digital charge-coupled shift registers are analyzed and their operation is demonstrated by charge-coupled circuits made by a p-MOS process. A charge-transfer efficiency of about 99.6 percent per electrode at a clock frequency of 1 MHz was obtained in... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan