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IEEE Journal of Solid-State Circuits

Issue 3 • June 1969

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Displaying Results 1 - 21 of 21
  • [Front cover - June 1969]

    Publication Year: 1969, Page(s): f1
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    Freely Available from IEEE
  • [Inside front cover - June 1969]

    Publication Year: 1969, Page(s): f2
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    Freely Available from IEEE
  • An outline of design techniques for linear integrated circuits

    Publication Year: 1969, Page(s):110 - 122
    Cited by:  Papers (18)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2188 KB)

    The components available in integrated circuits are well known for their large tolerances and temperature coefficients. This paper is a condensed survey of design principles that make use of the advantages offered in monolithic structures: close matching and tracking of parameters, control over component geometries, and the availability of a large number of active devices at little extra cost. Wit... View full abstract»

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  • An improved version of a floating gyrator

    Publication Year: 1969, Page(s):162 - 163
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (294 KB)

    A modified version (see abstr. B7204 of 1969) for the realization of gyrators with floating ports is proposed. When capacitor loaded the new circuit very accurately simulates a floating inductor without its being necessary for certain resistors to satisfy a symmetry condition, as was the case in the original circuit. View full abstract»

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  • A MOST integrated differential amplifier

    Publication Year: 1969, Page(s):166 - 168
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A monolithic MOST differential amplifier is described, having an input resistance of 10/SUP 11/-10/SUP 12/ ohms. The offset and drift, characteristic of present-day MOST's, are reduced to less than 2 mV by an offset correction circuit that retains the differential input capability. View full abstract»

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  • A p-n-p-n binary full adder

    Publication Year: 1969, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB)

    Describes the theory and design principle. By making use of the regenerative characteristics of p-n-p-n devices, a binary full adder circuit is designed. A computer-aided circuit analysis program is used to calculate circuit equations and to choose the external elements. The calculated response of the circuit agree with the experimental results. View full abstract»

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  • Notes on class-D transistor amplifiers

    Publication Year: 1969, Page(s):178 - 179
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB)

    Class-D operation of RF amplifiers is characterized by sinusoidal current and pulse-type voltage waveforms at the output of the active circuit element. It is suggested that this is a more accurate model for high-frequency large-signal transistor amplifiers than the conventional Class-C model. View full abstract»

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  • Contributors (June 1969)

    Publication Year: 1969, Page(s):179 - 180
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    Freely Available from IEEE
  • On the analogies between RGC distributed and the excess-minority- carrier transport circuits

    Publication Year: 1969, Page(s):172 - 174
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Gives a relation between the transport of excess-minority carriers in semiconductor materials and RGC distributed networks. It is shown that the matrix of the transport circuit can be decomposed into the product of two matrices. The first matrix has an analogical form as the matrix of a uniform or exponentially tapered RGC distributed network and the second one has the form of the matrix of a nonr... View full abstract»

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  • Theory and design of MOS capacitor pull-up circuits

    Publication Year: 1969, Page(s):145 - 158
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2248 KB)

    Capacitor pull-up circuitry is another addition to the numerous techniques the MOS engineer has available as a design tool. This `ratioless'-type circuit offers the potential advantage of high-speed two-phase operation. A complete circuit description and analysis is presented. Included in the analysis are topics covering bipolar injection effects, calculation of optimum size devices, stair-step ch... View full abstract»

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  • Improvement in the tetrode FET noise figure by neutralization and tuning

    Publication Year: 1969, Page(s):170 - 172
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The noise figure of the tetrode FET is calculated, and it is shown that for frequencies near the cutoff frequency of the FET a considerable improvement in noise figure is possible by neutralizing the drain-gate capacitance C/SUB dg/ of the first half of the tetrode and by tuning the interstage network between the first and second half of the tetrode FET. To make this improvement possible, the tetr... View full abstract»

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  • Low-light-level properties of the phototransistor charge-storage mode

    Publication Year: 1969, Page(s):136 - 144
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB)

    The phototransistor charge-storage or integration mode at low light levels is described accurately using a simple model. The base-emitter junction governs charge readout at low levels, causing very nonlinear circuit behavior. Sluggish transient response, increased sensitivity of output to transistor current gain, and a nonlinear transfer characteristic degrade phototransistor low-light-level behav... View full abstract»

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  • The circuit design management equation

    Publication Year: 1969, Page(s):168 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The current-switch emitter-follower circuit is used to demonstrate that (1) the circuit designer can reduce his problem to a simple linear algebraic expression, though it is somewhat difficult to obtain values for the terms of this equation with a high degree of accuracy, and (2) by making some simple substitutions in the designer's equation, the fundamental constraints on the design effort are re... View full abstract»

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  • Bucket-brigade electronics: new possibilities for delay, time-axis conversion, and scanning

    Publication Year: 1969, Page(s):131 - 136
    Cited by:  Papers (103)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    Deals with integrated analog shift register circuits. Analog information is stored in arrays or mosaics of very small capacitors and can be made to travel through the arrangement by charge transfer. The charge transfer is carried out by active elements located between the storage elements and controlled by a clock signal. The circuit presented is simple, feasible for integration, and suitable for ... View full abstract»

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  • Inductor simulation using a single unity gain amplifier

    Publication Year: 1969, Page(s):161 - 162
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A circuit consisting of a single unity gain amplifier, two resistors (R/SUB 1/,R/SUB 2/), and a capacitor (C) is presented for realization of a grounded inductor for integrated circuits. The circuit behaves as an inductor with inductance L=CR/SUB 1/R/SUB 2/ and maximum Q/SUB 0/=(R/SUB 1//R/SUB 2/)/SUP 1/2//2. Experimental results agree closely with the theoretical calculations. View full abstract»

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  • Technology and performance of integrated complementary MOS circuits

    Publication Year: 1969, Page(s):122 - 130
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1416 KB)

    The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test ... View full abstract»

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  • Intermittent failure problems of four-phase MOS circuits

    Publication Year: 1969, Page(s):107 - 110
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    A single four-phase MOS logic gate is capable of implementing a fairly complex Boolean function in a simple fashion. It is seen that a complex four-phase MOS gate exhibits certain circuit noise problems and peculiar transient behavior not observed in a simple four-phase MOS gate. The result of this noise can cause intermittent failures of the circuits. Solutions to the problems are discussed in th... View full abstract»

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  • Unijunction transistor model for computer circuit analysis

    Publication Year: 1969, Page(s):174 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Describes the development and verification of a mathematical model, including topology, defining equations, measurement techniques, and methods for extracting parameters which approximates the electrical characteristics of a unijunction transistor. The model is compatible with, and is designed to be used in, general computer circuit analysis programs. View full abstract»

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  • Rise time optimization of high-speed digital fanout circuits

    Publication Year: 1969, Page(s):159 - 161
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Rise times of digital fanout circuits consisting of current-switched transistor pairs are analyzed. It is shown that minimum rise time can be obtained by a finite number of stages having approximately identical current gains. In the limiting case when the rise time originates solely from the gain-bandwidth product of the transistors, the optimum current gain per stage is e/SUP 1/2/=1.65. View full abstract»

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  • Integrated-circuit implementation of direct-coupled gyrator

    Publication Year: 1969, Page(s):164 - 166
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Describes an integrated gyrator circuit that uses bipolar transistors, with a simulated inductance of 0.18 H and maximum Q factor of about 380 at 1 kHz. View full abstract»

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  • Intermodulation distortion of cascaded transistors

    Publication Year: 1969, Page(s):97 - 106
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1432 KB)

    Intermodulation distortion performance of cascaded transistors is analyzed using a nonlinear frequency-dependent model for the transistor and with Volterra series as an analysis tool. The objective of this study is to determine the optimum cascade that has high gain and good modulation performance especially for higher frequencies. A particular application is in long-haul, analog, solid-state coax... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com