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Solid-State Circuits, IEEE Journal of

Issue 2 • Date Dec. 1966

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Displaying Results 1 - 10 of 10
  • [Inside front cover - December 1966]

    Page(s): f2
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    Freely Available from IEEE
  • Table of contents (December 1966)

    Page(s): 73
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  • A Wide-Band UHF Logarithmic Amplifier

    Page(s): 74 - 81
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    Logarithmic amplifiers can be made using three basic techniques: nonlinear feedback, nonlinear loads, and successive detection. For very high-frequency, wide-band applications, the successive detection method is the most practical. This paper describes a logarithmic amplifier at UHF frequencies which uses this successive detection method. The design was made with simplicity, cost, and the minimum use of special instruction techniques as prime considerations. Development of a linear amplifier with an amplitude response flat within 3 dB from 380 to 1020 MHz is presented first. The method used to convert the linear amplifier to a logarithmic one is then shown. The result is a logarithmic amplifier with a transfer characteristic which is within /spl plusmn/ 1 dB of logarithmic over an input dynamic range of 40 dB. This amplifier is capable of responding to a 2.5 ns pulse-width RF pulse with a center frequency of 800 MHz. View full abstract»

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  • Integrated Conditioned OR and Inhibited OR Logic Circuits

    Page(s): 81 - 85
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    High-speed logic circuits capable of subnanosecond operation are described. The circuits may be constructed using monolithic transistor circuits and attached tunnel diodes, or entirely in hybrid integrated form. A capacitance isolation technique allowing the use of conventional monolithic current mode logic (CML) circuits in conjuction with tunnel diodes is also presented. This results in considerably increased speed and logic flexibility. With this approach, the potential low cost of monolithic circuits of large production volume and the high-speed capability of the tunnel diodes are both retained. Using commercially available tunnel diodes and monolithic circuits, average propagation delays of under 0.4 ns were achieved in an operating system. This represents about an order of magnitude improvement over speeds obtainable with monolithic circuits alone for an important class of logic functions. Good noise immunity is obtained since the tunnel diodes perform only the analog threshold OR operation. The described CONDITIONED OR and INHIBITED OR circuit family is logically complete; however, it is particularly suited for iterative logic. The circuit operation and characteristics are discussed in detail. Examples of their use are also given. View full abstract»

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  • Achieving Subnanosecond Delays Using Feedback with the Current Switch

    Page(s): 86 - 94
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    Beginning the basic current switch, the application of feedback is explored to achieve faster switching speeds with greater fanpower. This paper qualitatively describes the evolution of an integrated circuit that requires only one power supply and has, through the introduction of time-dependent negative feedback, achieved subnanosecond propagation delays with the ultimate speed limited primarily by the device used, the component tolerances, and the range of the operating environment. Higher input impedance, better stability and noise tolerance are also by-products of the circuit. From this analysis, a general logic family for high-speed computer applications may be derived. View full abstract»

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  • MOS Adaptive Memory Elements as Weights in an Adaptive Pattern Classifier

    Page(s): 94 - 99
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    A solid-state adaptive memory element compatible with integrated network circuitry and a pattern classifier employing the unique adaption properties of this element are described. Each individual element consists of a resistor, a diode, and a special purpose MOS transistor all fabricated on a silicon substrate. Adaption in this case is accomplished by changing the electrical characteristics of the MOS transistor. This element is combined with a fixed reference resistor in a current-summing scheme to form a useful adaptive weight having both positive and negative values. The circuitry necessary for controlling the adaption of the element and its use as a weight during pattern classification is relatively simple and completely compatible with established integrated circuit technology. The pattern classifier can easily be trained to classify the majority of a given group of input patterns correctly according to arbitrarily selected "desired outputs." View full abstract»

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  • Low Power Linear Circuits

    Page(s): 100 - 111
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    The importance of low power linear circuits in portable military communications and surveillance equipment has been expanding continually in recent years. Using optimum design techniques, the quiescent power requirements of many of these circuits-including low-frequency, wide-band, tuned, and low-noise amplifiers as well as oscillators, mixers, and detectors--frequently can be reduced by more than an order of magnitude compared with current practice. Three principal features of these optimum design techniques are: 1) the use of transistors whose maximum frequency capabilities are well beyond the range of direct interest for the circuit under consideration, 2) the selection of circuit configurations which demonstrate superior low power performance, and 3) the description of the quiescent power requirements of each circuit in terms of its primary small signal design constraints. Salient features of an FM helmet radio receiver designed for minimum power drain illustrate the optimum design techniques. View full abstract»

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  • The Synthesis of Integrable, Nearly Sinusoidal, Potentially Bistable Oscillators

    Page(s): 111 - 117
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    A procedure is given for the synthesis of a class of potentially bistable oscillator configurations which serve as proto-types for integrated, nearly sinusoidal applications. These oscillator configurations are synthesized by systematic addition of one- and two-port resistor-capacitor networks to integrable bistable circuits having two 3-terminal, charge-controlled, active devices. The procedure is based on the synthesis and embedding of open-circuit stable negative-resistance ports. The oscillators synthesized are conveniently classed as 2-, 3-, or 4-terminal oscillators and typical performance characteristics of lumped prototype and integrated realizations are given. Configuration synthesis is shown to enable the specification of properties which determine the ease of integrated realization (for example the nonisolated active device property). View full abstract»

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  • A Systems Approach to a Compatible Family of Linear Integrated Circuits

    Page(s): 118 - 122
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    An efficient and rapid technique for developing a compatible family of custom integrated circuits for systems applications is described. The approach makes use of a general purpose functional block which can be readily wired into a number of integrated circuit configurations. Wire bonded interconnections are used in place of the usual metallized interconnections. This permits a convenient form factor for "breadboarding" integrated circuits, while maintaining approximately the same parasitic interactions which will be present in the final designs. In this way, interface problems between functional electronic blocks can be studied as they relate to overall systems performance. Quick wiring changes may be made to modify the integrated circuits and optimize system performance. Final design layouts are then made in the conventional manner. As an example of the use of this technique, a general purpose block is described which was used to generate a compatible family of linear integrated circuits used in the Apollo-LEM lunar television camera. View full abstract»

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  • Contributors (December 1966)

    Page(s): 123 - 124
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan