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IEE Proceedings - Computers and Digital Techniques

Issue 5 • Sep 2002

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Displaying Results 1 - 6 of 6
  • Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm

    Publication Year: 2002, Page(s):229 - 239
    Cited by:  Papers (3)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (991 KB)

    The realisation of a real-time video-coding system calls for a dedicated motion-estimation architecture. Whereas all the existing motion-estimation architectures offer either computational speed or hardware simplicity, in this paper, the authors propose an efficient pipelined parallel architecture for the one-dimensional hierarchical search (1DHS) block-matching algorithm that is efficient in term... View full abstract»

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  • Exact minimisation of large multiple output FPRM functions

    Publication Year: 2002, Page(s):203 - 212
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (892 KB)

    The properties of the polarity for sum-of-products (SOP) expressions of Boolean functions are formally investigated. A transform matrix S is developed to convert SOP expressions from one polarity to another polarity. It is shown that the effect of SOP polarity is to reorder the on-set minterms of a Boolean function. Furthermore, the transform matrix P for fixed polarity Reed-Muller (FPRM) expressi... View full abstract»

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  • Neural network analysis for the identification of optimal variable orderings in the decomposition of complex logic functions

    Publication Year: 2002, Page(s):240 - 244
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (562 KB)

    An artificial neural network analysis is presented to predict the input variable Subsets that give efficient disjunctive decompositions of complex combinatorial logic functions. The subsets obtained match substantially with the optimum orderings from an exhaustive search for disjunctive decompositions. The subsets reveal significantly scaled down numbers of orderings in the search domain. The tech... View full abstract»

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  • SMTA: next-generation high-performance multi-threaded processor

    Publication Year: 2002, Page(s):213 - 218
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (624 KB)

    Multi-threading is one of the methods of improving the performance of processors. In this paper, a super-multi-threaded processor is proposed. In the multi-threaded architecture, a thread dispatcher is constructed to manage the thread-level parallelism and instruction-level parallelism, and to build a communication unit to transfer the dependence data among the threads. Furthermore, the authors il... View full abstract»

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  • High-performance compensation technique for the radix-4 CORDIC algorithm

    Publication Year: 2002, Page(s):219 - 228
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (776 KB)

    Although the full radix-4 CORDIC algorithm is efficient compared to the standard radix-2 version, the scale-factor overhead causes its improvement to be limited. In this work, an algorithm and its associated architecture have been proposed for parallel compensation of the scale factor for the radix-4 CORDIC algorithm in the rotation mode. The proposed method, which makes no prior assumptions about... View full abstract»

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  • Real-time fault-tolerant hypercube multicomputer

    Publication Year: 2002, Page(s):197 - 202
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (670 KB)

    A real-time fault-tolerant design for a d-dimensional hypercube multiprocessor with two modes of operation is presented and its reconfigurability is examined. The augmented hypercube, at stage one, has a spare node connected to each node of a subcube of dimension i, and the spare nodes are also connected as a (d-i)-dimensional hypercube. At stage two, the process is repeated by assigning one spare... View full abstract»

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