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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Issue 7 • Jul 2002

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Displaying Results 1 - 9 of 9
  • A generic multiple-feedback architecture and method for the design of high-order Σ-Δ modulators

    Publication Year: 2002, Page(s):465 - 473
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    In this paper, a generic multiple-feedback architecture associated with a systematic design method is proposed for the design of high-order Σ-Δ modulators. The goal of this approach is to determine the values of loop coefficients of a designed modulator with limited coefficient ratios for easy integrated-circuit implementation, while achieving high signal-to-noise ratio (SNR) and a wid... View full abstract»

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  • AM-to-PM conversion in varactor-tuned oscillators

    Publication Year: 2002, Page(s):509 - 513
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    This brief deals with AM-to-PM noise conversion due to varactors and nonlinear capacitances. The effect increases the sensitivity of oscillators to substrate and power supply noise and sets a serious limitation to the phase noise performance of these stages when they are embedded in complete transceivers. A rigorous approach to the quantitative estimate of the conversion factor and a closed-form e... View full abstract»

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  • A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter

    Publication Year: 2002, Page(s):449 - 456
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1220 KB) | HTML iconHTML

    In this paper, a reconfigurable pipeline analog-to-digital converter (ADC) architecture is proposed. Based on dynamic performance measurements, the best performance configuration will be chosen from a collection of possible configurations. A 40-MSample/s 9-b reconfigurable pipeline ADC is designed and implemented in Taiwan Semiconductor Manufacturing Corporation's (TSMC's) 0.25-μm single-poly C... View full abstract»

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  • Efficient DDD-based symbolic analysis of linear analog circuits

    Publication Year: 2002, Page(s):474 - 487
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB) | HTML iconHTML

    The general framework of a symbolic analysis environment for linear time-invariant circuits is presented. Such a framework consists of two major parts: a simplification at circuit level and a simplifying expression-generation. An overview of the known techniques for both circuit simplification and expression generation is given, and in addition a new nonhierarchical expression generation technique... View full abstract»

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  • A 37 mW fully integrated GMSK modulator for DRRS standard in 0.6-μm digital CMOS process

    Publication Year: 2002, Page(s):513 - 520
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB) | HTML iconHTML

    A prototype Gaussian minimum key shifting (GMSK) modulator for digital radio relay systems (DRRSs) standard without any external component has been designed and simulated in the 1.4 GHz frequency band in a 0.6 μm CMOS process. The modulator including a compensation filter allows digital frequency modulation at 1.6 Mb/s. Using a low-power frequency divider and a low-power low-phase noise oscilla... View full abstract»

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  • Programmable interleaver design for analog iterative decoders

    Publication Year: 2002, Page(s):457 - 464
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (553 KB) | HTML iconHTML

    Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of... View full abstract»

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  • A low power VLSI architecture for mesh-based video motion tracking

    Publication Year: 2002, Page(s):488 - 504
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1581 KB) | HTML iconHTML

    This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduc... View full abstract»

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  • Time-stretched ADC arrays

    Publication Year: 2002, Page(s):521 - 524
    Cited by:  Papers (9)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB) | HTML iconHTML

    This brief analyzes the performance of a new type of analog-to-digital converters (ADCs) architecture. The approach contemplates stretching the analog signal in time prior to digitization. Its benefits include an increase in the effective sampling rate and the input bandwidth, and a reduction in the sampling-jitter noise of the digitizer. It builds on the recent demonstration of high-speed analog-... View full abstract»

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  • Analysis of a half-rate bang-bang phase-locked-loop

    Publication Year: 2002, Page(s):505 - 509
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB) | HTML iconHTML

    This brief presents the timing analysis of a half-rate phaselocked loop (PLL) with a bang-bang phase detector. The lock-in behavior of the PLL is discussed and parameters such as jitter, lock-in frequency range, and lock-in time are calculated. Behavioral simulation is used to validate the analytical results with particular emphasis on the PLL lock-in behavior. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope