By Topic

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 7 • Date Jul 2002

Filter Results

Displaying Results 1 - 9 of 9
  • Analysis of a half-rate bang-bang phase-locked-loop

    Publication Year: 2002 , Page(s): 505 - 509
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    This brief presents the timing analysis of a half-rate phaselocked loop (PLL) with a bang-bang phase detector. The lock-in behavior of the PLL is discussed and parameters such as jitter, lock-in frequency range, and lock-in time are calculated. Behavioral simulation is used to validate the analytical results with particular emphasis on the PLL lock-in behavior. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Programmable interleaver design for analog iterative decoders

    Publication Year: 2002 , Page(s): 457 - 464
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (553 KB) |  | HTML iconHTML  

    Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of 100, as opposed to full crossbars, while maintaining full programmability. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A generic multiple-feedback architecture and method for the design of high-order Σ-Δ modulators

    Publication Year: 2002 , Page(s): 465 - 473
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    In this paper, a generic multiple-feedback architecture associated with a systematic design method is proposed for the design of high-order Σ-Δ modulators. The goal of this approach is to determine the values of loop coefficients of a designed modulator with limited coefficient ratios for easy integrated-circuit implementation, while achieving high signal-to-noise ratio (SNR) and a wide range of maximum dc input levels. The proposed method uses the transfer function of a structure-matched filter as an initial solution to synthesize the transfer function of a designed modulator. By using mapping and scaling techniques, 4 to 6 dB larger SNR, two to three times greater range of maximum dc input level, and ten to 1000 times smaller coefficient ratio than those of conventional methods and structures are obtained by the proposed architecture and method. Simulation results show that a minimum of 110-dB SNR is attained for modulators with order higher than four, as tested over a 20-kHz audio bandwidth at a sampling rate 2.56 MHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient DDD-based symbolic analysis of linear analog circuits

    Publication Year: 2002 , Page(s): 474 - 487
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (547 KB) |  | HTML iconHTML  

    The general framework of a symbolic analysis environment for linear time-invariant circuits is presented. Such a framework consists of two major parts: a simplification at circuit level and a simplifying expression-generation. An overview of the known techniques for both circuit simplification and expression generation is given, and in addition a new nonhierarchical expression generation technique based on the concept of determinant decision diagrams (DDDs) is presented. The DDD-based technique is evaluated on a set of benchmark circuits together with a known fast symbolic analysis algorithm, and turns out to be the most efficient. The DDD-based expression generation algorithm is, therefore, the best solution for nonhierarchical linear symbolic expression generation to the authors' knowledge. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • AM-to-PM conversion in varactor-tuned oscillators

    Publication Year: 2002 , Page(s): 509 - 513
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    This brief deals with AM-to-PM noise conversion due to varactors and nonlinear capacitances. The effect increases the sensitivity of oscillators to substrate and power supply noise and sets a serious limitation to the phase noise performance of these stages when they are embedded in complete transceivers. A rigorous approach to the quantitative estimate of the conversion factor and a closed-form expression are derived. The conversion due to typical varactor structures available in integrated technology is discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 37 mW fully integrated GMSK modulator for DRRS standard in 0.6-μm digital CMOS process

    Publication Year: 2002 , Page(s): 513 - 520
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB) |  | HTML iconHTML  

    A prototype Gaussian minimum key shifting (GMSK) modulator for digital radio relay systems (DRRSs) standard without any external component has been designed and simulated in the 1.4 GHz frequency band in a 0.6 μm CMOS process. The modulator including a compensation filter allows digital frequency modulation at 1.6 Mb/s. Using a low-power frequency divider and a low-power low-phase noise oscillator, the power consumption of the modulator is minimized. Transistor and system level simulations demonstrate that the modulator meets the performance requirements of the DRRS standard. Circuit simulation with a 0.6 μm CMOS technology shows that the power consumption of the modulator is 37 mW from a 3 V power supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power VLSI architecture for mesh-based video motion tracking

    Publication Year: 2002 , Page(s): 488 - 504
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1581 KB)  

    This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and uses a parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter

    Publication Year: 2002 , Page(s): 449 - 456
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1220 KB) |  | HTML iconHTML  

    In this paper, a reconfigurable pipeline analog-to-digital converter (ADC) architecture is proposed. Based on dynamic performance measurements, the best performance configuration will be chosen from a collection of possible configurations. A 40-MSample/s 9-b reconfigurable pipeline ADC is designed and implemented in Taiwan Semiconductor Manufacturing Corporation's (TSMC's) 0.25-μm single-poly CMOS digital process. The chip is measured for all the configurations under different temperatures to prove the reconfiguration will provide significant effective number of bits (ENOB) improvement among the set of configurations. The active area of the design is 5.9 mm2. The power consumption is 425 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Time-stretched ADC arrays

    Publication Year: 2002 , Page(s): 521 - 524
    Cited by:  Papers (6)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    This brief analyzes the performance of a new type of analog-to-digital converters (ADCs) architecture. The approach contemplates stretching the analog signal in time prior to digitization. Its benefits include an increase in the effective sampling rate and the input bandwidth, and a reduction in the sampling-jitter noise of the digitizer. It builds on the recent demonstration of high-speed analog-to-digital (A/D) conversion where a photonic preprocessor was used to successfully stretch an analog electrical signal before electronic digitization. The brief considers parallel time stretch ADC arrays capable of processing continuous time signals. In particular the effects of interchannel offset and gain mismatch, and clock skew are described and are contrasted with those in a conventional time-interleaved system. A mode of operation unique to this system is outlined wherein interchannel mismatch errors are entirely avoided at the expense of resolution bandwidth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope