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IEEE Transactions on Computers

Issue 12 • Date Dec 1990

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Displaying Results 1 - 13 of 13
  • Adaptive fault-tolerant routing in hypercube multicomputers

    Publication Year: 1990, Page(s):1406 - 1416
    Cited by:  Papers (97)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    A connected hypercube with faulty links and/or nodes is called an injured hypercube. A distributed adaptive fault-tolerant routing scheme is proposed for an injured hypercube in which each node is required to know only the condition of its own links. Despite its simplicity, this scheme is shown to be capable of routing messages successfully in an injured n-dimensional hypercube as long as... View full abstract»

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  • Sequential fault occurrence and reconfiguration in system level diagnosis

    Publication Year: 1990, Page(s):1472 - 1475
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    In a classical system-level diagnosis model, a complex multiprocessor system is characterized to be uniquely diagnosable under the presence of any arbitrary fault set of size up to t. Fault occurrence, however, is usually a sequential process in real-life systems, i.e. multiple faults occur one after another. Any faulty location is immediately diagnosed and the system is reconfigured befo... View full abstract»

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  • Modular architecture for high performance implementation of the FRR algorithm

    Publication Year: 1990, Page(s):1464 - 1468
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A novel VLSI-oriented architecture to compute the discrete Fourier transform is presented. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/t transforms per second, where t is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever... View full abstract»

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  • Embedding rectangular grids into square grids with dilation two

    Publication Year: 1990, Page(s):1446 - 1455
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A novel technique, the multiple ripple propagation technique, is presented for mapping and h×w grid into a w ×h grid such that the dilation cost is 2, i.e. such that any two neighboring nodes in the first grid are mapped onto two nodes in the second grid that are separated by a distance of at most 2. The technique is then used as a basic tool for map... View full abstract»

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  • On the constant diagnosability of baseline interconnection networks

    Publication Year: 1990, Page(s): 1458
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    A novel approach for the diagnosis of baseline interconnection networks with a fan-in/fan-out of 2 is presented. The totally exhaustive combinatorial fault model with single fault assumption is used in the analysis. Some new characteristics of baseline interconnection networks are proved. A characterization for the fault location and the fault type of the one-response fault are given. This charact... View full abstract»

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  • On addition and multiplication with Hensel codes

    Publication Year: 1990, Page(s):1417 - 1423
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    It has been stated by R.N. Gorgui-Naguib and R.A. King (1986) that the operations of addition and multiplication on Hensel codes originally defined by E.V. Krishnamurthy, T.M. Rao, and K. Subramanian (1975) are seriously in error in that it is possible to add/subtract or multiply Hensel codes and not get a valid Hensel code. It is shown that it is the presence of so-called invalid Farey fractions ... View full abstract»

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  • An upper bound on expected clock skew in synchronous systems

    Publication Year: 1990, Page(s):1475 - 1477
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A statistical model is considered for clock skew in which the propagation delays on every source-to-processor path are sums of independent contributions, and are identically distributed. Upper bounds are derived for expected skew, and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two special cases of clock distribut... View full abstract»

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  • A simulation-based method for generating tests for sequential circuits

    Publication Year: 1990, Page(s):1456 - 1463
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    In a recent work of the authors (1987), a simulation-based directed search approach for generating test vectors for combinational circuits was proposed. In this method, the search for a test vector is guided by a cost function computed by the simulator. Event-driven simulation deals with circuit delays in a very natural manner. Signal controllability information required for the cost function is i... View full abstract»

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  • Radix-16 signed-digit division

    Publication Year: 1990, Page(s):1424 - 1433
    Cited by:  Papers (17)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    A two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm uses two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit. The algorithm requires a two-digit estimate of the (initial) partial remainder and a three-digit estimate of the divisor to correctly select each successive quotient digit. The normalization... View full abstract»

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  • A reconfigurable tree architecture with multistage interconnection network

    Publication Year: 1990, Page(s):1481 - 1485
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching fro... View full abstract»

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  • Fault detection and design complexity in C-testable VLSI arrays

    Publication Year: 1990, Page(s):1477 - 1481
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    An extension of a previous approach to fault detection and C -testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test... View full abstract»

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  • Parallel graph algorithms based upon broadcast communications

    Publication Year: 1990, Page(s):1468 - 1472
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    Some common guidelines that can be used to design parallel algorithms under the single-channel broadcast communication model are presented. Several graph problems are solved, including topological ordering, the connected component problem, breadth-first search, and depth-first search. If an ideal conflict resolution scheme is used, all of the algorithms require O(n) time by using... View full abstract»

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  • The performance of parallel Prolog programs

    Publication Year: 1990, Page(s):1435 - 1445
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB)

    Performance results are presented for a parallel execution model for Prolog that supports AND-parallelism, OR-parallelism, and intelligent backtracking. The results show that restricted AND-parallelism is of limited benefit for small programs, but produced speedups from 7-10 on two large programs. OR-parallelism was found to be generally not useful for the benchmarks examined if the semantics of P... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org