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IEEE Transactions on Computers

Issue 11 • Date Nov 1990

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Displaying Results 1 - 13 of 13
  • The testability of generalized counters under multiple faulty cells

    Publication Year: 1990, Page(s):1378 - 1385
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    The testability of a class of circuits called generalized counters is investigated under a more powerful fault model than examined in earlier work. It is assumed that any number of full adders in a generalized counter can assume an incorrect function under fault, as long as the function remains combinational. The testability of the overall class of generalized counters is examined and it is shown ... View full abstract»

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  • Analyzing scheduled maintenance policies for repairable computer systems

    Publication Year: 1990, Page(s):1309 - 1324
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1436 KB)

    A solution method is developed to analyze various scheduled maintenance policies for repairable computer systems. The analysis is applicable to systems with behavior (exclusive of the scheduled maintenance policy) that can be modeled by a continuous-time Markov process, and thus important characteristics can be included in the model. Furthermore, the assumption of perfect repair, which is unrealis... View full abstract»

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  • Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition

    Publication Year: 1990, Page(s):1359 - 1368
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting a... View full abstract»

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  • A systematic (12,8) code for correcting single errors and detecting adjacent errors

    Publication Year: 1990, Page(s):1403 - 1404
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A parity check matrix is given for a systematic (12,8) binary code which connects all single errors and detects eight of the nine double adjacent errors within any of the three 4-b nibbles. It is shown that no (12,8) binary systematic parity check code can correct all 12 single errors and simultaneously detect all nine double adjacent errors within 4-b nibbles. A (12,8) binary systematic parity ch... View full abstract»

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  • The organization of permutation architectures with bused interconnections

    Publication Year: 1990, Page(s):1346 - 1358
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1184 KB)

    The problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations is explored. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, it is shown that the number of pins per chip can often be reduced. As an example, for infinitely many n, the authors exhibit permutation architectures that can... View full abstract»

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  • Group theoretic signature analysis

    Publication Year: 1990, Page(s):1398 - 1403
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A new class of data-compression techniques called group-theoretic signature analysis (GTSA) for testing a logic network is proposed, and the fault coverage of the method is analyzed. This method is a generalization of accumulator compression testing. Built-in-self-test for processor environments is feasible with GTSA View full abstract»

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  • An architecture for addition and subtraction of long word length numbers in the logarithmic number system

    Publication Year: 1990, Page(s):1325 - 1336
    Cited by:  Papers (45)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    An architecture is described for performing addition and subtraction of numbers in the logarithmic number system using small lookup tables. Previous implementations require approximately 4×2 F words for F bits of precision in the fraction. The author shows how to reduce the size of the lookup table to fewer than (18+F)×2F/2 words. The key to this... View full abstract»

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  • On computing signal probability and detection probability of stuck-at faults

    Publication Year: 1990, Page(s):1369 - 1377
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    Algorithms for the following two problems are presented: (1) computing detection probability of stuck-at faults (CDP), and (2) computing signal probability (CSP). These problems arise in the context of random testing, pseudorandom testing, and testability analysis of combinational circuits. The algorithm for CDP combines the notion of supergates and a refinement of th algorithm for CDP presented i... View full abstract»

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  • An analysis of scatter decomposition

    Publication Year: 1990, Page(s):1337 - 1345
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A formal analysis of a powerful mapping technique known as scatter decomposition is provided. Scatter decomposition divides an irregular computational domain into a large number of equally sized pieces and distributes them modularly among processors. A probabilistic model of workload in one dimension is used to formally explain why and when scatter decomposition works. The first result is that if ... View full abstract»

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  • Fast multiplication without carry-propagate addition

    Publication Year: 1990, Page(s):1385 - 1390
    Cited by:  Papers (54)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right... View full abstract»

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  • Fast, deterministic routing, on hypercubes, using small buffers

    Publication Year: 1990, Page(s):1390 - 1393
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A deterministic routing scheme for a communications network based on the k-dimensional hypercube is proposed. The author presents two formulations of the scheme. The first formulation delivers messages in O(k2) bit times using O(K ) bits of buffer space at each node in the hypercube. The second formulation assumes that there are several batch... View full abstract»

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  • An interconnection network for distributed recursive computations

    Publication Year: 1990, Page(s):1393 - 1395
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Distributed computations may be viewed as a set of communicating processes. If such a computation is to be executed by a multiprocessor system, the processes have to be distributed over the processors, and the communications have to be distributed over a network. This leads to the questions of load balancing and message routing. The authors consider distributed recursive computations and propose a... View full abstract»

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  • Area minimization in a three-sided switchbox by sliding the modules

    Publication Year: 1990, Page(s):1395 - 1398
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    An optimal algorithm for minimizing the number of columns (width) in a three-sided switchbox, when the modules are allowed to slide, is presented. The proposed algorithm runs in O(mn+e log e) time, where m and n are the number of terminals on the top and on the bottom, and e is the total number of feasible alignments (e⩽... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org