IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Jul 1988

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Displaying Results 1 - 8 of 8
  • An interchange format for process and device simulation

    Publication Year: 1988, Page(s):741 - 754
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    A standard format for transmitting profiles of semiconductor structures between sites and between tools is described. The standard, called the profile interchange format (PIF), is a flexible and hierarchical format, capable of storing descriptions of semiconductor structures such as those produced and used by process and device simulators. It can store detailed descriptions of the geometry, attrib... View full abstract»

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  • On the simplification of a placement problem

    Publication Year: 1988, Page(s):805 - 812
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    The authors consider the placement of heterogeneous modules to minimize the expected value of the distance required for an intermodule communication, where the expectation is taken with respect to a given matrix of intermodule communication probabilities. One way the placement problem could be simplified would be to select a `footprint' with the property that all modules of the optimum placement o... View full abstract»

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  • Generalized Manhattan path algorithm with applications

    Publication Year: 1988, Page(s):797 - 804
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The author presents an efficient algorithm for finding a route interconnecting two terminals of arbitrary polygonal shape in two layers. The main feature of the router to be distinguished from the existing grid-free routers is that it can handle large vias. The author has also considered the extension to multi-terminal nets and demonstrate a native algorithm which repeats the same path finding pro... View full abstract»

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  • Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography

    Publication Year: 1988, Page(s):755 - 764
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    Etchant percolation through voids plays an important role in dissolution of radiation sensitive materials in IC manufacture, but analysis and simulation of this phenomenon are hampered by the complexity of carrying out simulations at up to 20000 voids etching simultaneously. An attempt is made to use a simplified material crack model and a formulation of the model in terms of cellular automata, wh... View full abstract»

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  • A method of fault analysis for test generation and fault diagnosis

    Publication Year: 1988, Page(s):813 - 833
    Cited by:  Papers (120)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1632 KB)

    The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on t... View full abstract»

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  • Fast functional simulation: an incremental approach

    Publication Year: 1988, Page(s):765 - 774
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    In an effort to speed up simulation, a novel algorithm,, called incremental simulation evaluates the circuit components that can be affected directly or indirectly by design changes, utilizing the information generated during the previous simulation to reduce the number of component evaluations to a minimum. The authors describe the design and implementation of the incremental algorithm for logic ... View full abstract»

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  • Analysis and synthesis of combinational pass transistor circuits

    Publication Year: 1988, Page(s):775 - 786
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    A method for analyzing a wide range of CMOS pass transistor circuits is presented. Based on concepts derived from analysis, synthesis algorithms are proposed. They have been implemented as a program called PAVOS which can solve relatively complex problems. A manual method is presented for handling simpler ones. An effective minimization of the circuit area is obtained by using incomplete transmiss... View full abstract»

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  • Optimum design of IC power/ground nets subject to reliability constraints

    Publication Year: 1988, Page(s):787 - 796
    Cited by:  Papers (20)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    The authors formulate and solve the problem of sizing power/ground (p/g) nets in integrated circuits composed of modules, where the nets are routed as trees in the channels between the modules. Constraints are developed to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule requirements. The objective is to minimize the area of the p/g ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu