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IEEE Design & Test of Computers

Issue 5 • Oct. 1990

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Displaying Results 1 - 4 of 4
  • From behavior to structure: high-level synthesis

    Publication Year: 1990, Page(s):8 - 19
    Cited by:  Papers (31)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    This paper shows how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools, such as logic synthesis and layout. As opposed to logic synthesis, which optimizes only combinational logic, high-level synthesis deals with memor... View full abstract»

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  • An optimizer for hardware synthesis

    Publication Year: 1990, Page(s):20 - 36
    Cited by:  Papers (13)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1245 KB)

    A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its i... View full abstract»

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  • The Olympus synthesis system

    Publication Year: 1990, Page(s):37 - 53
    Cited by:  Papers (86)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1348 KB)

    A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of su... View full abstract»

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  • Neural net and Boolean satisfiability models of logic circuits

    Publication Year: 1990, Page(s):54 - 57
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB)

    Two recently proposed models of digital circuits that are useful in parallel test-generation methods are described. In the neural net model, the input and output signal states of a logic gate are related through an energy function. In the Boolean satisfiability model, a logic gate is represented by a truth expression. How the equivalence of these models offers the flexibility of using the same alg... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty