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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 5 • Date May 2002

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Displaying Results 1 - 8 of 8
  • A polyphase IIR adaptive filter

    Page(s): 356 - 359
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB)  

    A polyphase structure for infinite-impulse response (IIR) adaptive filtering is proposed and compared to the direct structure in terms of their reduced error surface. It is shown that the general shape of its surface can make the polyphase structure have higher convergence speed, alleviating the problem of convergence speed in IIR adaptive filters and allowing their computational complexity gain over finite-impulse response (FIR) adaptive filters to be exploited. Benefits regarding filter stability are also achieved with the polyphase structure. An example of a high-speed digital subscriber line (HDSL) application is presented, for which the polyphase structure attains a gain of up to 70 times in convergence speed over an IIR direct structure, leading to roughly the same convergence speed of a FIR structure but with only 12% of its computational complexity. The question of uniqueness of the stationary points of the proposed structure is also discussed. It is pointed out that for white input and sufficient modeling, all stationary points are global minima, a result which does not follow directly from an equivalent property of the direct structure. View full abstract»

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  • Analog VLSI neural network with digital perturbative learning

    Page(s): 359 - 368
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    Two feed-forward neural-network hardware implementations are presented. The first uses analog synapses and neurons with a digital serial weight bus. The chip is trained in loop with the computer performing control and weight updates. By training with the chip in the loop, it is possible to learn around circuit offsets. The second neural network also uses a computer for the global control operations, but all of the local operations are performed on chip. The weights are implemented digitally, and counters are used to adjust them. A parallel perturbative weight update algorithm is used. The chip uses multiple, locally generated, pseudorandom bit streams to perturb all of the weights in parallel. If the perturbation causes the error function to decrease, the weight change is kept; otherwise, it is discarded. Test results from a very large scale integration (VLSI) prototype are shown of both networks successfully learning digital functions such as AND and XOR. View full abstract»

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  • Analysis of power recycling techniques for RF and microwave outphasing power amplifiers

    Page(s): 312 - 320
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB) |  | HTML iconHTML  

    A power recycling technique has been analyzed for efficiency-enhanced radio-frequency (RF) and microwave outphasing power amplifiers for mobile wireless communications. By use of a simple power recycling network, a considerable portion of the wasted power can be recovered back to the power supply, and the enhancement of the overall power efficiency can be achieved without sacrificing the high-linearity performance of the amplifier system. An analysis and calculations have been conducted to optimize the recycling network for maximum power efficiency. The results predict a significant improvement on the overall power efficiency of the amplifier system for various modulations. View full abstract»

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  • Spectral analysis of time-domain phase jitter measurements

    Page(s): 321 - 327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    A simplified overview of time-domain jitter measurements is presented in this paper. The relationship between the time-domain jitter measurements and the power spectrum of the phase jitter is described using fundamental Fourier properties and basic random variables analysis. This leads to a unifying analysis and the results are in agreement with commonly accepted understanding of jitter accumulation in oscillators. The presented analysis also provides the basis for comparing different jitter measurements. View full abstract»

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  • Improved switched tuning of differential CMOS VCOs

    Page(s): 352 - 355
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    Varactors for continuous frequency tuning are typically used in LC-oscillators. However, they have some drawbacks for large tuning ranges, such as high tuning sensitivity causing high sensitivity to noise and disturbances on the control voltage. Furthermore, large metal-oxide-semiconductor (MOS) varactors have high conversion of harmless amplitude noise into harmful phase noise. To reduce these problems a small varactor can be used in combination with MOS-transistors that switch fixed capacitors in and out of the oscillator. The limitations due to the imperfect complementary metal-oxide-semiconductor (CMOS) switches are investigated, and an improved structure for use with the popular differential CMOS LC-oscillator is presented. View full abstract»

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  • Automatic calibration of modulated frequency synthesizers

    Page(s): 301 - 311
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (391 KB) |  | HTML iconHTML  

    This paper describes a new approach to the automatic calibration of modulated phase-locked loop (PLL) frequency synthesizers. The new calibration approach tunes the response of the PLL while the synthesizer is in service and compensates for process and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation of sigma-delta (Σ-Δ) frequency synthesizers. The calibration method can be applied to Gaussian frequency shift keying (GFSK), Gaussian minimum shift keying (GMSK) modulation, and also M-ary FSK modulation. A low-frequency board level prototype has been constructed to validate the calibration approach. View full abstract»

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  • An approach to switching activity consideration during high-level, low-power design space exploration

    Page(s): 339 - 351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB)  

    A novel approach is introduced that exploits characteristics of fixed-point, two's complement data in order to reduce power consumption related to switching activity. This approach is based on an intuitive switching activity model that captures the most essential data characteristics with statistical parameters. The approach is embodied in a heuristic that uses the model to systematically reduce switching activity of interconnect between data path units. The perspective provided by the model and heuristic allows efficient and intuitive high-level design space exploration. This approach is demonstrated through an example of high-level design space exploration for a low power processor dedicated to implementing the IS-54 vector-sum excited linear predictive (VSELP) speech codec. Application of the heuristic results in up to 56% activity reduction at high energy locations in the data path and estimated processor power reduction of about 15% on average during encoding compared to an obvious implementation. View full abstract»

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  • Design of low-phase-noise CMOS ring oscillators

    Page(s): 328 - 338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope